问题描述
假设我有一个寄存器 REG [15：0] my_reg ，它包含一个16位的签署示例：
Assuming I have a register reg [15:0] my_reg, which contains a 16-bit signed sample:
我如何把样品从符号到无符号？
我已阅读和我认识的2位补为有符号数，但我怎么用Verilog有效地执行这种转换？
（我不知道，如果 my_reg 为正或negatve，并且在每一个时钟周期的变化=我收到的每个时钟上升沿新的样品）。
How do I convert the sample from signed to unsigned?I have read this Wikipedia article, and am aware of the 2-bit complement for signed numbers, but how do I perform this conversion in Verilog efficiently?(I don't know if my_reg is positive or negatve, and it changes in every clock cycle = I receive a new sample on every positive clock edge).
终极目标（添加上下文的一点点）是实现数字FPGA内置自动增益控制（AGC）。
The ultimate goal (to add a little bit of context) is to implement a digital FPGA built-in automatic gain control (AGC).
编辑：的建议我已经一分为二不同岗位的两个问题。看到另一个here
as suggested I have split the two questions in two different posts. See the other one here
推荐答案
在Verilog的reg中包含二进制数据，签署无符号仅仅是间pretation的问题。该位值保持使用补总是执行相同的，加法和减法。
In Verilog a reg contains binary data, signed unsigned are just a matter of interpretation. The bit values stay the same, subtraction and addition are always performed using two's complement.
例如，我们可以看一个4位的值，看看这些数字如何可除preTED：
For example, we can look at a 4 bit value and see how the numbers can be interpreted:
Binary Unsigned signed
1000 8 -8
1110 14 -2
1111 15 -1
0001 1 1
0010 2 2
0111 7 7
我觉得你要到一个积极的规模，这些数字校准，-8变为0，0变成8,7变成15.这将通过来完成的到MSB位置加入1 即可。在我们的4位例如：
I think you want to calibrate these numbers on to a positive scale, -8 becomes 0, 0 becomes 8, 7 becomes 15. This would be done by adding 1 in to the MSB position. In our 4 bit example:
Binary Signed Addition Unsigned result
1000 -8 +1000 0000 0
1110 -2 +1000 0110 6
1111 -1 +1000 0111 7
0001 1 +1000 1001 9
0010 2 +1000 1010 10
0111 7 +1000 1111 15
有一些密切相关的问题：结果
1. 结果。
补码比较 2. Verilog的建设。
There are some closely related questions:
1. Verilog: how to take the absolute value.
2. Verilog Construction of Two's Complement Comparator.
如果您的注册确实包含签约信息，然后语义，你应该把它定义为：
If your register really does contain signed information then semantically you should define it as :
reg signed [15:0] my_reg;
要绝对的值：
reg signed [15:0] my_reg;
reg [15:0] my_reg_unsigned;
always @* begin
if (my_reg < 16'd0) begin
my_reg_unsigned = -my_reg ;
end
else begin
my_reg_unsigned = my_reg ;
end
end
如果您不需要绝对的，但只是想用这个数字来推动一些东西它是有效的签署只是连接到一个无符号，例如：
If you do not need to absolute it but just want to use that number to drive some thing it is valid to just connect signed to an unsigned, ie:
always @* begin
my_reg_unsigned = my_reg ;
end
这将复制位值， my_reg_unsigned 可PTED为使用签订间$ P $ $符号（my_reg_unsigned）
This will copy the bit values, my_reg_unsigned can be interpreted as signed using $signed(my_reg_unsigned)
这篇关于签署的Verilog符号VS样品和第一的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！