问题描述
在其他问题中，我问我有关于我的模块的一般建议。
现在我在这里寻求建议，因为我注意到Verilog社区有更多的用户。
In this other question I asked I got some general advice regarding my module.Now I seek advice here since I noted that the Verilog community has more users.
我试图将现有的框架实现为最高有效位）操作。
这个想法如下：我从中获取旧 / code>，而不是MSB操作。
I have searched this problem in SE and found some good explanations on what might be going wrong, here or here for example.What I understand is the following: temp_buff <= {i_msb,q_msb,temp_buff[31:24]}; is a conflictive line since the <= operator is getting the old values from i_msb and q_msb, and not the ones from the MSB operation.
（2）我尝试避免 if-else 条件允许我从永远@ * 块中声明一些东西（这样我避免在LHS上有一条线一个总是块，这是不允许的）。
(2) I tried avoiding if-else conditions to allow me to declare some things out of the always @* block (this way I avoid having a wire on the LHS of an always block, which is not allowed).
我的条件是否正确？
如前所述，我只想要分配每个第四个 bb_sample 。
是 assign bb_strobe =（count == 2'd3）？ 1'b1：1'b0; 得到我想要的效果，尽管不在总是@（posedge时钟）块？
Are my conditionals correct?As I explained before, I want only every 4th bb_sample to be assigned.Is assign bb_strobe = (count==2'd3) ? 1'b1 : 1'b0; getting the effect I want despite not being in the always @(posedge clock) block?
如果需要其他信息，请让我知道。这是我为了目的而修改的更大的项目的一部分。
推荐答案
（1）修剪的FF / Latch警告不是由于非阻塞分配。来自 temp_buff 寄存器的24位始终分配给零。 RHS为16位; （4位），（4位），$ code>（4位）和 temp_buff [31:24 ] （8位）。并且您将其分配给32位值。作业：
(1) The trimmed FF/Latch warning is not due to non-blocking assignments. It is from 24 bits of the temp_buff register always being assigned to zeros. The RHS is 16bits; i_msb (4 bits), q_msb (4 bits), and temp_buff[31:24] (8 bits). And you are assigning it to a 32bit value. The assignment:
temp_buff <= {i_msb,q_msb,temp_buff[31:24]};
相当于：
temp_buff <= {16'h0000, i_msb,q_msb,temp_buff[31:24]};
这意味着 temp_buff [31:16] 将始终为零可以优化出来。 temp_buff [7：0] 也可以优化为常量零，因为它被分配到 temp_buff [31:24] 这是一个常数0.也许你的意思是你右移8位，如下所示：
This means temp_buff[31:16] will always be zero can can be optimized out. temp_buff[7:0] can also be optimized out to constant zeros because it is assigned to temp_buff[31:24] which is a constant 0. Perhaps you meant you shift right 8 bits like so:
temp_buff <= {i_msb,q_msb,temp_buff[31: 8 ]};（2）正确的是，不应该为任何总线（或初始块）分配电线。但是，您可以将线转到 reg 。这是一个错误的概念， reg 仅用于寄存器（FF /锁存器）。编码组合块中的 reg 将创建组合逻辑（无FF或锁存）。 属性表示在每个分支条件下使用always块分配 reg ，否则它推断出一个锁存器。示例
(2) You are correct that wires should not be assigned with any always block (or initial block). However you could have turned the wire to a reg. It is a miss conception that reg is for registers only (FF/Latches). reg in a properly coded combinational block will create combinational logic (no FF or Latches). Property meaning the reg is assigned within every branching condition withing the always block, else it infers a latch. Example
module my_rx_dsp0_custom
/* ... your original code ... */
output reg [31:0] bb_sample,
output reg bb_strobe //high on valid sample
);
/* ... your original code ... */
always @(posedge clock)
if(ddc_out_strobe) begin
temp_buff <= {i_msb,q_msb,temp_buff[31:8]};
count <= (count==2'd3) ? 2'd0 : (count+1);
end
always @*
begin
i_msb = ddc_out_sample[31:28];
q_msb = ddc_out_sample[15:12];
bb_strobe = (count==2'd3);
bb_sample = bb_strobe ? temp_buff : 32'd0;
end
assign ddc_out_enable = enable;
/* ... your original code ... */
这篇关于Verilog中的Xilinx警告（FF / Latch修整），用于MSB下采样的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！