问题描述
有一个体面的指南，说明如何使用TLB（翻译后援缓冲器的）上的 ARM1176JZF-S 核心表？
说完看了看的是ARM平台的技术文档我仍然不知道一个TLB是什么，或者什么样子。据我了解，每一个TLB项的虚拟页面映射到物理页，允许重映射和控制内存的权限。
除此之外，我对如何使用它们丝毫没有线索。
- 没有一个TLB项有什么结构？如何创建新的项目？
- 如何处理虚拟机的上下文切换用户空间线程？我如何确保这些线程只能访问分配给他们的父进程特定页面（执行内存保护的）？难道我救TLB状态为每个上下文？
- 为什么有两个TLB的？我可以使用什么MicroTLB因为如果它只能有10个条目？当然，我需要超过10个。
- 它说，主TLB的部分之一就是八素的全关联数组，这是可锁定。那是什么？难道我只能得到有8项主TLB？
谢谢你在前进。我来，如果有人提供了什么样的TLB是一个解释是真的很高兴。我目前工作的一个内存映射为我的内核，我已经pretty多少进入了死胡同。
有关ARM1176JZF-S的技术参考手册似乎是DDI 0301该文件包含所有特定ARM内核的具体细节。
A TLB is a cache of the page table. Some processors allow direct access to the TLB, while knowing nothing about page tables (e.g: MIPS), while others know about page tables, and internally use TLBs that the programmer mostly doesn't see (e.g: x86). In this case, the TLB is managed by hardware, and the system programmer only has to care to make the TTB (Translation Table Base) registers point to the page table, and invalidate the TLB in apropriate places.
Done by hardware. On a TLB miss, the MMU walks the page table and fills the TLB from there.
Some platforms have TLBs that simply map virtual addresses to physical addresses (e.g: x86). On these platforms, you have to do a full TLB flush on each context switch. Other platforms (MIPS, this specific ARM core) map (ASID, virtual address) pairs to physical addresses. An ASID is an Application-Specific Identifier, i.e: an identifier for a process. The MMU uses a register to know which ASID to use (I think it's the Context ID register in this case). Since there may be more processes than ASIDs, occasionally you may need to recycle an ASID (assigning it to a different process) and do a TLB flush (that's what the Invalidate TLB by ASID operation is for).
This is exactly for the same reason you have small separate level-1 caches for instructions and data. Since they are caches, you don't need more than 10 (though having more could improve performance).
Some memory pages (e.g: some portions of the kernel) are accessed very often. It makes sense to lock them, so they don't get thrown off of the TLB. Also, on realtime systems, a TLB miss or a cache miss may introduce some unwanted unpredictability. So, there is an option to lock a number of TLB entries. The main TLB has more entries, but only those 8 are lockable.
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