使用端口映射的4位加法器

问题描述

所以我试图做一个4位加法器，却遇到了一个我似乎无法弄清的错误.

So I am trying to do a 4 bit adder and have ran into an error I can't seem to figure out.

错误(10430):在adder1.vhd(3)处发生VHDL主单元声明错误:库"work"中已经存在主单元"Adder1Vhd"

Error (10430): VHDL Primary Unit Declaration error at adder1.vhd(3): primary unit "Adder1Vhd" already exists in library "work"

我有一个名为4位加法器的项目，该项目文件夹中是Adder1.vhd的.vhd文件.这是我的代码，如果有人可以帮助我解决这个问题，将不胜感激.

I have a project called 4 bit adder and inside that project folder is the .vhd file for Adder1.vhd. Here is the codes I have, if somebody could help me figure this out it would be greatly appreciated.

Adder4.vhd:

Adder4.vhd:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Adder4 IS
  GENERIC(CONSTANT N: INTEGER := 4);
  PORT(
    a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Input SW[7..4]: a[3..0] inputs,
                                             -- SW[3..0]: b[3..0]
    cIn: in std_logic;
    sum: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Output LEDR[3..0]
    cOut: OUT STD_LOGIC -- Output LEDR[4]
  );
END Adder4;

ARCHITECTURE imp OF Adder4 IS
  COMPONENT Adder1
    PORT(
      a, b, cIn : in STD_LOGIC;
      sum, cOut : out STD_LOGIC);
  END COMPONENT;
  SIGNAL carry_sig: std_logic_vector(N-1 DOWNTO 0);
BEGIN

  A1: Adder1 port map (a(0), b(0), cIn, sum(0), carry_sig(0));
  A2: Adder1 port map (a(1), b(1), carry_sig(0), sum(1), carry_sig(1));
  A3: Adder1 port map (a(2), b(2), carry_sig(1), sum(2), carry_sig(2));
  A4: Adder1 port map (a(3), b(3), carry_sig(2), sum(3), cOut);

END imp;

Adder1.vhd(Adder4项目文件夹中的文件):

Adder1.vhd(the file inside the Adder4 project folder):

library ieee;
use ieee.std_logic_1164.all;

entity Adder1Vhd is
  port(
    a, b, cIn : in std_logic;
    sum, cOut : out std_logic);
end Adder1Vhd;

architecture imp of Adder1Vhd is
begin
  -- Add two lines (one for sum and the other for cOut) of VHDL code here
  sum <= (a xor b) xor cIn;
  cOut <= (a and b) or (cIn and (a xor b));
end imp;

推荐答案

在库工作(当前工作库)中，还有另一个文件具有名为 Adder1Vhd 的实体.您可以删除磁盘上的文件，也可以仅将其从Quartus II的文件导航器中的库工作中删除.

There is another file that has an entity named Adder1Vhd in the library work (current work library). You can either delete the file on disk or just remove it from the library work in the file navigator of Quartus II.

顺便说一句，使用与实体相同的名称保存VHDL文件是一个很好的约定.

By the way, it's a good convention to save a VHDL files using the same name as the entity.

并且组件的名称必须是其实体的名称，而不是文件名.因此，

And the name of a component must be the name of it's entity, not the filename. So,

COMPONENT Adder1  -- here 'Adder1' should be 'Adder1Vhd'
  PORT(
    a, b, cIn : in STD_LOGIC;
    sum, cOut : out STD_LOGIC);
END COMPONENT;

组件实例化语句相同.

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