Verilog减法和加法

问题描述

我正在尝试在Verilog中编写加法和减法程序.问题是在执行加法或减法的模块的Verilog中实现和测试，然后Mux在让一个或另一个的结果通过之间进行选择，然后将所选结果从二进制解码为7段显示格式. Verilog模块将具有3个输入:两个名为A和B的4位输入，以及一个选择输入S.您的电路应将两个数字相加，并且还应从A中减去B(就像在代码中包含A-B一样简单).根据S的值(即是1还是0)，您应该让加法的结果或减法的结果通过.

I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of a module that performs Addition or Subtraction, then a Mux chooses between letting go through the result of one or the other, and then Decode the selected result from binary into a 7-segment Display format. Verilog Module will have 3 inputs: two 4-bit inputs named A and B, and a select input S. Your circuit should add the two numbers and should also subtract B from A (it is as simple as having A-B in your code). Depending on the value of S (i.e. whether it’s a one or a zero), you should let either the result of the addition or the result of the subtraction through.

这是我拥有的代码: 模块AddOrSubtractThenSelectAndDecodeInto7SegmentsDisplay(A，B，S，Result，Overflow，Display);

This is the code that I have: module AddOrSubtractThenSelectAndDecodeInto7SegmentsDisplay(A,B,S,Result,Overflow,Display);

input [3:0] A;
input [3:0] B;
input [1:0] S;

output reg [3:0] Result;
output reg Overflow;
output reg [6:0] Display;

wire [3:0] A;
wire [3:0] B;
wire [1:0] S;



always @(A,B) begin
    if (S == 0'b0)
        {Overflow, Result} = A - B;
    else if (S == 1'b1)
        {Overflow, Result} = A + B;
    end

always @(Overflow,Result) begin
    case (Result)
        4'b0000: Display = 7'b1111110;//0
        4'b0001: Display = 7'b0110000;//1
        4'b0010: Display = 7'b1101101;//2
        4'b0011: Display = 7'b1111001;//3
        4'b0100: Display = 7'b0110011;//4
        4'b0101: Display = 7'b1011011;//5
        4'b0110: Display = 7'b1011111;//6
        4'b0111: Display = 7'b1110000;//7
        4'b1000: Display = 7'b1111111;//8
        4'b1001: Display = 7'b1111011;//9
        4'b1010: Display = 7'b1110111;//A
        4'b1011: Display = 7'b0011111;//B
        4'b1100: Display = 7'b1001110;//C
        4'b1101: Display = 7'b0111101;//D
        4'b1110: Display = 7'b1001111;//E
        4'b1111: Display = 7'b1000111;//F
        default: Display = 7'bx;
    endcase

    if (Overflow == 1)begin
        Result = 4'bx;
        Display = 7'b0011101;
    end
end


endmodule

当我运行讲师测试台时，除显示外，所有行均为绿色.它显示Display [6:0] xxxxxxx，后跟红线.我花了2天的时间来解决此问题.有什么帮助吗?

When I run the instructors test bench all the lines are green except for display. It says Display[6:0] xxxxxxx and followed by red lines. I have spent 2 days looking at this trying to fix it. Any help please?

推荐答案

一行看起来很奇怪:

if (S == 0'b0)

基本上，这意味着零位为零".在verilog中，我认为格式为位´b 值.

Basically that means "number zero with zero bits". In verilog I think the format is bits´bvalue. Replace the b with h for hex format (and use google for rest of the options ;))

就像其他张贴者所说的那样，尽管仅使用了MSB， S 似乎是2位向量.

Also like said by other posters, S seems to be 2bit vector though only the MSB is used.

x 值在现实世界中也不存在-这只是模拟器说"I dunno"的一种方式.这样就无法合成.

And also the x value does not exist in real world - it's just a way for the simulator to say "I dunno". So that will not synthesize.

否则，我看不到在不同的Always块中同一信号被分配两次以上的情况?当在同一块中完成时，应该没问题.后一个值仅覆盖前一个值. Google提供 blocking 和 non-blocking 以获得更多信息.

Otherwise I fail to see where the same signal is assigned more than twice in different always blocks? When done in the same block it should be ok. The latter value just overrides the previous one. Google for blocking and non-blocking for more info.

编辑:您还用什么作为刺激?如果A和B是静态的，它们将不会引起事件，而该事件又不会导致始终块触发.因此，输出保持在7'bx.对此不太确定，但值得检查.

edit: also what do you use as the stimulus? If A and B are static, they will not cause an event which in turn causes none of the always blocks to fire. Hence the output stays in 7'bx. Not really sure about this, but worth to check.

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