问题描述
在以下代码中:首先，我在给定地址加载带有数据和权重的 ROM.在同一个时钟中，我正在做数据和权重的乘法.最后，我将位数从 16 位扩展到 23 位.代码编译没有错误，但有警告.我无法解决这些警告.
In the following code: First, I am loading ROM with data and weight at given address. In the same clock I am doing multiplication of data and weight. Finally, I am extending the number of bits from 16-bit to 23-bit. The code compiles without errors but has warnings. I am unable to solve these warnings.
module main_module(extended_out,mux_out,data,weight,clk,en,addr);
input clk,en;
input [2:0] addr;
output [7:0] data,weight;
output [15:0] mux_out;
output [22:0] extended_out;
ram_input a1 (clk, en, addr, data);
ram_weight a2 (clk, en, addr, weight);
top_module a3 (mux_out,data,weight);
SignExtender a4 (clk,mux_out,extended_out);
endmodule
################## 模块 1 #######################################
module ram_input (clk, en, addr, data);
input clk;
input en;
input [2:0] addr;
output reg [7:0] data;
reg [2:0] raddr;
always @(posedge clk)
begin
if (en)
raddr <= addr;
end
always @(raddr,en)
begin
if (en)
begin
case(raddr)
3'b000: data = 8'b0000_0010;
3'b001: data = 8'b0000_0110;
3'b010: data = 8'b0000_1110;
3'b011: data = 8'b0000_0010;
3'b100: data = 8'b0000_0100;
3'b101: data = 8'b0000_1010;
3'b110: data = 8'b0000_1100;
3'b111: data = 8'b0000_0000;
default: data = 8'b0000_XXXX;
endcase
end
else
data = 8'b0000_0000;
end
endmodule
#################################### 模块 2 ########################
module ram_weight (clk, en, addr, weight);
input clk;
input en;
input [2:0] addr;
output reg [7:0] weight;
reg [2:0] raddr;
always @(posedge clk)
begin
if (en)
raddr <= addr;
end
always @(raddr,en)
begin
if (en)
begin
case(raddr)
3'b000: weight = 8'b0000_1000;
3'b001: weight = 8'b0000_1010;
3'b010: weight = 8'b0001_1101;
3'b011: weight = 8'b0001_0100;
3'b100: weight = 8'b0000_0111;
3'b101: weight = 8'b0001_0010;
3'b110: weight = 8'b0010_1000;
3'b111: weight = 8'b0011_1111;
default: weight = 8'b0000_XXXX;
endcase
end
else
weight = 8'b0000_0000;
end
endmodule
###########################33 MODULE--3 #####################
module top_module(p,x,y);
output [15:0]p;
input [7:0]x,y;
reg [15:0]p;
reg [15:0]a;
integer i;
always @(x , y)
begin
a=x;
p=0;
for(i=0;i<8;i=i+1)
begin
if(y[i])
p=p+a;
a=a<<1;
end
end
endmodule
############################模块----4 #############################
module SignExtender( clk, extend, extended );
input[15:0] extend;
input clk;
output[22:0] extended;
reg[22:0] extended;
wire [15:0] extend;
always @( posedge clk)
begin
extended[22:0] <= { {7{extend[15]}}, extend[15:0] };
end
endmodule
############################## 错误####################
警告 646 - 信号a"已分配但从未使用.这个未连接的信号将在优化过程中被修剪.
WARNING 646 - Signal "a" is assigned but never used. This unconnected signal will be trimmed during the optimization process.
警告 1710 - FF/Latch a4/extended_15"(无初始值)在块 main_module 中的常量值为 0.这个FF/Latch会在优化过程中被修整.
WARNING 1710 - "FF/Latch a4/extended_15" (without init value) has a constant value of 0 in block main_module. This FF/Latch will be trimmed during the optimization process.
警告:Xst:1895 - 由于其他FF/Latch 修整"，FF/Latcha4/extended_14"(没有初始值)在块main_module"中有一个常数值 0.这个FF/Latch会在优化过程中被修整.
WARNING:Xst:1895 - Due to other ""FF/Latch trimming"", FF/Latch ""a4/extended_14"" (without init value) has a constant value of 0 in block "main_module". This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - 由于其他 FF/Latch 修整，FF/Latch ""a4/extended_13""(无初始值)在块 ""main_module"" 中具有恒定值 0.这个FF/Latch会在优化过程中被修整.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch ""a4/extended_13"" (without init value) has a constant value of 0 in block ""main_module"". This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - 由于其他 FF/Latch 修整，FF/Latch ""a4/extended_12""(无初始值)在块 ""main_module"" 中具有恒定值 0.这个FF/Latch会在优化过程中被修整.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch ""a4/extended_12"" (without init value) has a constant value of 0 in block ""main_module"". This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - 由于其他 FF/Latch 修整，FF/Latch ""a4/extended_11""(无初始值)在块 ""main_module"" 中具有恒定值 0.这个FF/Latch会在优化过程中被修整.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch ""a4/extended_11"" (without init value) has a constant value of 0 in block ""main_module"". This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - 由于其他 FF/Latch 修整，FF/Latch ""a4/extended_10""(无初始值)在块 ""main_module"" 中具有恒定值 0.这个FF/Latch会在优化过程中被修整.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch ""a4/extended_10"" (without init value) has a constant value of 0 in block ""main_module"". This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - 由于其他 FF/Latch 修整，FF/Latch ""a4/extended_0""(无初始值)在块 ""main_module"" 中具有恒定值 0.这个FF/Latch会在优化过程中被修整.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch ""a4/extended_0"" (without init value) has a constant value of 0 in block ""main_module"". This FF/Latch will be trimmed during the optimization process.
warning--1 说你没有使用常量a"变量但是在做乘法时我把它当作一个临时寄存器但是剩下的错误我不明白他们真正要说什么...
warning--1 says you didn't use constant "a" variable but while doing multiplication I took as an temporary register but remaining errors I don't understand what they really going to tell...
请帮助解释这些警告.
推荐答案
你的基本问题可能是 top_module 中的 p=p+a.这没有意义；尝试绘制原理图.这是一个组合路径，加法器的输出反馈到其输入.去掉它，把 ，根据 的相关位加在一起y.这可能足以让您继续前进.
Your basic problem is probably the p=p+a in top_module. This doesn't make sense; try to draw the schematic. This is a combinatorial path with the output of an adder fed back to its input. Get rid of it, and just add together the , depending on the relevant bit of y. This may be enough to get you going.
编辑
你的代码不太可能(正确地)合成(无论如何，任何理智的合成器).考虑一下:
Your code is unlikely to be (correctly) synthesisable (by any sane synthesiser, anyway). Consider this:
always @(x , y)
begin
a=x;
p=0;
for(i=0;i<8;i=i+1)
begin
if(y[i])
p=p+a;
a=a<<1;
end
end
这是组合代码.您要求合成器展开您的 i 循环.每次 x 或 y 更改时，您希望合成器评估所有 8 次循环迭代，移位 a，并累加到 p.合成器通常非常擅长循环展开，但这个人正在推动它.摆脱循环，无论您认为 XST 是否理解它；这只是不好的做法，可能会混淆 XST.在纸上画一个示意图.您所做的只是移动 a:您有一个未修改的 a，以及 7 个 a 被移动 1 到 7 位的实例.您需要一个将所有 8 条总线相加的加法器，但是如果设置了 y 的相应位，则您只能在总线 i 中添加.换句话说，加法器的每个输入都有一个多路复用器；一个输入保持为零，另一个是您移位的 a.您需要自己编写代码.这就是您进行硬件设计的方式:将所有内容分解为基本单元 - 多路复用器、移位器、加法器等等，并将它们连接在一起.不要编写您的合成器必须尝试为您解决的行为代码；那是软件，而不是硬件.
This is combinatorial code. You are asking the synthesiser to unroll your i loop. Every time x or y changes, you want the synthesiser to evaluate all 8 loop iterations, shifting a, and accumulating to p. Synthesisers are normally pretty good at loop unrolling, but this one is pushing it. Get rid of the loop, whether or not you think XST understands it; it's just bad practice, and is probably confusing XST. Draw a schematic on paper. All you're doing is shifting a: you've got one unmodified a, and 7 instances where a is shifted by 1 to 7 bits. You need an adder which adds together all 8 busses, but you only add in bus i if the corresponding bit of y is set. In other words, each input to the adder has a multiplexer on it; one input is held to zero, the other is your shifted a. You'll need to write the code yourself. This is how you do hardware design: break everything down into basic units - multiplexers, shifters, adders, whatever, and wire them togehter. Don't write behavioural code that your synthesiser has to try to work out for you; that's software, not hardware.
Greg 可能是对的，您的实际电路可以根据您的实际输入条件进行简化，并且无论如何该电路最终都不会被使用；确认这一点不是 5 分钟的工作，而且无论如何也毫无意义.您正在尝试编写乘法器，而您的输入条件会发生变化，您需要正确编写代码.XST 可能会，也可能不会，计算出在任何特定情况下它都可以简化逻辑，但您必须先修复输入代码.
Greg may be right in that your actual circuit can be simplified according to your actual input conditions, and that this circuit is eventually unused anyway; it's not a 5-minute job to confirm that, and it's pointless anyway. You're trying to write a multiplier, and your input conditions will change, and you need to get the code right. XST may, or may not, be able to work out that in any particular situation it can simplify the logic, but you have to fix your input code first.
您还有其他问题.不要像 Don't Cares 那样将 X 分配给您的变量.这是非常糟糕的做法，会出错.阅读 Mike Turpin 的论文等.简而言之，除非您确切地知道自己在做什么，否则永远不要使用 X.在 x/y always 块中使用非阻塞赋值.可能还有其他问题，但在快速通读时并不明显.
You have other issues. Don't assign X's to your variables as Don't Cares. This is very bad practice, and will go wrong. Read Mike Turpin's paper, among others. In short, never use X's unless you know exactly what you're doing. Use non-blocking assignments in the x/y always block. There may be other issues, which aren't obvious on a very quick read-through.
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