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问题描述

我正在对内存数据库进行一些研究,想知道哪种类型的应用程序将从内存数据库的可预测延迟特性中获得最大收益.

I'm doing some research on In-Memory databases and am wondering what type of applications would benefit the most from the predictable latency characteristic of In-Memory databases.

我可以想象在线游戏,例如第一人称射击游戏.我只是在想什么其他类型的应用程序.

I can imagine online gaming, such as first person shooter games. I'm just wondering what other type of applications.

推荐答案

受益于可预测的延迟(无论延迟与否,延迟抖动都困扰着……)的应用程序不足为奇了

Not much surprisingly the very applications, that benefit from predictable latency (be it low, or not -- latency jitter bothers...)

低延迟边缘:

HPC ,其中纳秒级和亚纳秒级的延迟最为重要,这是因为计算复杂性的规模巨大(超出Peta,Exa,...前缀的静态比例),其中所有RAM数据结构内处理的保证性确定性 latency启用了 true PARALLEL 而不仅仅是-基于尽力而为" 的CONCURRENT代码执行中的机会主义信念.

DSP ,在这里您根本承受不起阻止/等待" ,但会损失唯一的&几乎不可重复的信号流(可以想象CERN的LHC信号传输到实验数据信号传感器的读数/数据采集记录/数据控制+健全性/实验控制+处理/存储服务)

low-latency edge:

HPC, where nanoseconds and sub-nanosecond delays matter most, due to immense scale of the computational complexity ( static scales beyond Peta, Exa, ... prefixes ), where a guarranteed determinism of all In-RAM data-structure handling latency enables true PARALLEL and not just-an-opportunistic-belief in "best-efforts" based CONCURRENT code-execution.

DSP, where you simply cannot afford to "block/wait" at a cost of missing the next part of the unique & hardly repeatable signal-flow ( may imagine a CERN's LHC signals to experimental data signal-sensor readings / data-acquisition recording / data-conditoining + sanity / experiment control + processing / storage services )

中延迟区:

"hard" real-time constrained control systems (F-35航空电子设备,可以使原本固有的不稳定飞机保持在蓝天的上方(足够快)在许多离散的状态之间的,基于传感器网络的+脉冲控制的执行器触发状态转换的完全协调无限循环,共同起草了我们人类习惯于称之为飞行"的行为的信封"错觉(而飞机无法飞行" (是的,它无法扩展它是自己的运动状态,并且在距当前状态,因为那样会导致不经意的机头向下挖/平旋失速...您将其全部命名为),

类似的操作系统,确定性调度程序,音频/视频实时流p处理器,

telephone switching (嗯,最近移动接入网的分组无线广播延迟抖动有点歪曲了全球TELCO的先进性网络同步性,开发了80多个独立实体/90多个独立实体,但所有这些主要都是基于定义的延迟阈值,并且由于具有将日本PDH系统的日本标准与美国无缝​​连接的功能而首次被降低-PDH层次结构与旧大陆的ISDN/PDH层次结构的标准,否则,相互之间无法单独连接.参考有关详细信息,请参见SDH/SONET体系结构. )

mid-latency zone:

"hard" real-time constrained control systems ( F-35 avionics, that keeps otherwise inherently unstable aircraft somewhere up in the blue skies by ( fast enough ) fully coordinated endless-loop of sensor-network-based + pulse-controlled-effectors'-triggered state-transitions between many discrete states, that collectively draft an "envelope" illusion of a behaviour that we humans are used to call flying ( while the aircraft is not able to "fly" ( yes, it cannot extend it's own state-of-motion and continue in such motion any few moments further from any current state because that would cause an inadvertent nose-down dig / flat-spin stall ... you name it all ),

"soft" real-time systems alike operating systems, deterministic schedulers, audio/video live-stream processors,

telephone switching ( well, recent packet-radio latency jitter of the mobile access networks a bit skew the advances of global TELCO networks synchronicity, developed over 80-ies/90-ies, but all these were principally building on defined latency tresholds and alowed for the first time due to this very feature to seamlessly connect Japan-standards of their PDH systems with US-standards of PDH hierarchy with the old continent's ISDN / PDH hierarchies, that were otherwise mutually impossible to connect on their own. Ref. to SDH/SONET architecture for details. )

高延迟区域:(是的,延迟并不不利 ( if kept under control ) ))

SoC 设计,其中足够"原则在可用资源的最边缘处控制基于约束的系统设计,即以最少的处理器资源和最少的DRAM供电预算部署系统,使用最少的物料清单/ASIC设计,同时受益于已知的确定性等待时间,这可确保您的"足够"设计仍然符合要求的稳定性部署的处理程序的可靠性,而代价却是最小的.

high-latency zone: ( yes, high latency is nothing adverse ( if kept under control ) )

SoC-designs, where "just-enough" principle rules the constraint-based system design, at the very edge of the resources available -- i.e. deploy the system with minimum processor resources, with minimum DRAM-powering budget, with minimum Bill-of-Material / ASIC designs, while benefiting on the fact of a known, deterministic, latency, which ensures your "just-enough" design will still meet the required stability & reliability of the deployed processing at a minimised cost of that.

作者并没有不知不觉地(有意无意地)陷入任何行话或杂乱的标签中.上面文本中使用的术语在当代IT和TELCO领域中很常见,因为字母表是普通读者中使用的术语.当然,任何专业化专业都会添加更多的标签和缩写,这些标签和缩写没有其他机会,只能与其他科学,技术或人类活动领域的首字母缩略词共享首字母缩略词的出现,但这是付出的代价.组成首字母缩写词.

Author has not either un-knowingly, the less intentionally, slipped into any jargon or strange tags juggling. The terms used in the text above are as common in the contemporary IT and TELCO domains, as alphabet is among the general audience. Sure, any professional specialisation adds plenties of more tags and abbreviations, that have no other chance but share acronyms' appearance with other, similarly looking acronyms from other field of science, technology or other field of humans' activity, but this is the cost of composing acronyms.

因此,在任何科学和/或工程领域中,首字母缩略词正切"的妥善护理是一种常见的做法.

Due care with acronym meaning dis-ambiguation is thus a common practice in any scientific and/or engineering domain.

上面的文本使用了一些很常见的术语:

The text above has used a few terms, that are pretty common:

DSP :数字信号处理
CERN :ConseilEuropéenpour la RechercheNucléaire
LHC :大型强子对撞机,是地球上最大的已知粒子加速器(CERN,CH)
F-35 :洛克希德·马丁公司生产的F-35 JSC飞机
> SoC :片上系统-Xilinx ZynQ,FPGA s,EpiphanyIV MPPA,Kalray Bostan2(R)等
ASIC :专用集成电路

DSP: Digital Signal Processing
CERN: Conseil Européen pour la Recherche Nucléaire
LHC: Large Hadron Collider, a largest known particle accelerator on the Earth ( CERN, CH )
F-35: Lockheed Marting F-35 JSC aircraft
SoC: System-on-Chip -- Xilinx ZynQ, FPGAs, EpiphanyIV MPPA, Kalray Bostan2(R) et al
ASIC: Application Specific Integrated Circuit

HPC :高性能计算是所有与计算相关的科学的前沿/流血边缘-硬件,软件,计算问题可计算性背后的理论基础(Big-O评分) (ref.complex-theory))

HPC: High-Performance Computing is a leading/bleeding edge of all the computation-related sciences -- hardware, software, theoretical foundations behind the computational problems' computability ( Big-O rating ( ref. complexity-theory ) )

nanosecond = 1 / 1.000.000.000 秒.

nanosecond = 1 / 1.000.000.000 fraction of a second.

当代电视广播和{CRT|LED}-monitor-刷新率
大约需要 1 / 24 .. 1 / 60 秒(即大约40.000.000 - 20.000.000 ns).

Contemporary TV-broadcasting and {CRT|LED}-monitor-refresh rates
take about 1 / 24 .. 1 / 60 second ( i.e. about 40.000.000 - 20.000.000 ns ).

这就是说,当代最快的CPU时钟大约是 5.000.000.000 [Hz] .

This said, the fastest contemporary CPU-clocks are about 5.000.000.000 [Hz].

这意味着,
这样的单个CPU内核可以计算
大约 200.000.000 单个-CLK CPU-指令,
下一个视觉输出(图片)应完成并显示在屏幕上.

That means,
such single CPU-core can compute
about 200.000.000 single-CLK CPU-instructions,
before a next visual-output ( a picture ) shall get finished and put on screen.

这确实为基础游戏引擎提供了大量的时间来计算/处理所需的任何东西.

That provides indeed a vast amount of time for underlying gaming-engine to compute / process whatever needed.

恰恰相反,在大量的二进制流的高强度计算和/或高容量传输中(超级计算和电信网络等),这种这么长时间的舒适感并不常见.

On the very contrary, such comfort of having that much time is not so common in high-intensity computing and/or high capacity transport of binary streams ( super-computing and telecommunication networks et al ).

在外部触发的处理中,任何这样的假设都是公平的,在这种情况下,事件交织不受控制,并且原则上是不确定的. HFT 交易领域就是这样的简短示例,其中必须尽可能降低延迟,因此内存技术是唯一可行的方法.

The less is any such assumption fair in externally triggered processing, where events interleaving is not under ones control and is principally non-deterministic. HFT trading realm is such brief example, where lowest-possible latencies are a must, so in-Memory technology is the only feasible approach.

即使是低强度HFT交易软件也没有足够的时间,因为
10%的事件到达的时间少于+__100 [ms]
20%的事件到达的时间少于+__200 [ms]
30%的事件到达的时间少于+1 100 [ms]
40%的事件到达的时间少于+1 200 .. +200 000 [ms]-其余事件到达的时间在1.2 and 200 [sec]

Even low-intensity HFT-trading software does not have plenty of time as
10% of events arrive in less than +__100 [ms]
20% of events arrive in less than +__200 [ms]
30% of events arrive in less than +1 100 [ms]
40% of events arrive in less than +1 200 .. +200 000 [ms] -- the rest arrives in anything between 1.2 and 200 [sec]

(有关延迟控制软件设计的更多详细信息超出了本S/O帖子的格式,但是可视化演示和ms,us和ns的定量比较可用于任何类型的计算,希望可以显示此信息-延迟感知软件设计的主要区别)

( deeper details on controlled-latency software design exceed the format of this S/O post, but visual demonstrations and quantitative comparison of ms, us and ns available for any kind of computation hopefully shows the message -- the key difference for a latency-aware software design )

要想一想,当代硬件中一个CPU/一个CPU集群/一个CPU网格可以执行多少计算步骤,而花费少于 10 ns . > CPU 可以从 DRAM 读取值,小于 0.1 ns 可以从on- CPU-缓存内存.

To have some idea, how many computing steps a CPU / a cluster-of-CPUs / a grid-of-CPUs may undertake in contemporary hardware spends less than about 10 ns for CPU to read a value from DRAM, less than about 0.1 ns to fetch a value from on-CPU-cache-memory.

尽管CPU上的高速缓存大小不断增长(今天,常见的消费类电子产品,处理器的规格状态为 { L2 | L3 }高速缓存大小大于20 MB ,这是您的考虑因素 (我的第一台PC拥有的硬盘驱动器容量已经超过了我的能力(而高科技产品是在 COCOM 出口法规,要求重新批准并禁止 Cold-War 禁止在Western Block领土以外的任何潜在出口)缓存分配算法没有提供将整个数据库存储在(缓存)内存中的先验确定性.

While on-CPU-cache sizes are growing ( and today specifications state for common, consumer electronics, processors { L2 | L3 }-cache sizes above 20 MB, which is for your kind consideration more than my first PC used to have available as it's Hard Disk Drive capacity ( and that high-tech piece was those days under supervision of COCOM export regulations, requiring approval for re-export and having a Cold-War ban to disable any potential export outside of Western Block territories ) cache-allocation algorithms are not providing an a-priori deterministic certainty of having the whole database in-(cache)-memory.

因此,最快的访问权限大约是 0.1 ns local CPU-cache ,但这并不确定.

So, the fastest access is about 0.1 ns into local CPU-cache, but it is uncertain.

下一个最快的访问方式是大约 10 ns local DRAM 内存中,并且 GB .. TB 大小可以放入此内存类型.

The next fastest access is about 10 ns into local DRAM memory, and GB .. TB sizes can fit into this memory-type.

下一个最快的访问方式是大约 800 ns NUMA 分布式内存基础架构中,其中 1 000 TB .. 1 000 000 TB 可以容纳的容量( Peta Bytes到Exa Bytes)和全部,在统一的且可预测的访问时间大约为800 ns 的情况下得到服务(对于这样的大型数据库,等待时间变得尽可能低,并且既一致又可预测).

The next fastest access is about 800 ns into NUMA distributed memory infrastructures, where capacities above 1 000 TB .. 1 000 000 TB can fit ( Peta Bytes to Exa Bytes ) and all be served under a uniform and predictable access times of about the 800 ns ( the latency becomes both lowest possible for such huge databases and is both uniform and predictable ).

因此,如果说的确实是较低且可预测的延迟,那么这些是衡量延迟的标准.

So, if speaking about indeed a low and predictable latency these are the yardsticks that measure it.

CAPEX OPEX 这样的高容量+高性能计算框架的成本(用来评估任何专业购买计算技术的费用)是非常高昂的,到目前为止,文明还没有更好的计算引擎.

Both CAPEX and OPEX costs ( by which any professional purchase of computing technology is assessed ) of such high-capacity + high-performance computing frameworks are very prohibitive, but human civilisation has no better computational engines so far.

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07-23 00:43
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