停车场闸门仿真中的未知值(X)

问题描述

我正在用VHDL语言设计一个停车场闸门。当我使用Quartus VWF文件模拟它时，我得到了未知值(X)，但我不知道原因。

基本上，您只需验证您的卡(Sin)，大门就会打开10秒。而当一辆车离开停车场(Sout)时，它会统计停车场内此刻的车辆总数。我已经为计时器创建了信号Ncarros(计算车数)和s_count。

都可以正确编译。但是当我使用VWF文件测试它时，我得到的是：

Original simulation output

我正在使用Altera Quartus Prime Lite Edition。

有人能检查我的代码并告诉我哪里做错了吗？

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity MicroProj is
    port (clk      : in std_logic;
            Sin      : in std_logic;
            Sout     : in std_logic;
            cancela  : out std_logic;
            timerOut : out std_logic);

end MicroProj;

architecture Behavioral of MicroProj is

    signal Ncarros : integer := 0;
    signal s_count : integer := 0;

begin
    process (Sin,Sout,clk)
    begin
        if (Sin = '0') then
            cancela <= '0';
        else
            if (Ncarros < 99) then
                Ncarros <= Ncarros + 1;
                cancela <= '1';

                if(rising_edge(clk)) then
                    if(s_count /= 0) then
                        if(s_count = 499999999) then
                            timerOut <= '1';
                            s_count <= 0;
                        else
                            timerOut <= '0';
                            s_count <= s_count + 1;
                        end if;
                    else
                        timerOut <= '0';
                        s_count <= s_count + 1;
                    end if;
                end if;
            end if;
        end if;

        if (Sout ='1') then
            Ncarros <= Ncarros - 1;
        end if;
    end process;


end Behavioral;

Quartus

当您使用矢量波形文件进行模拟时，推荐答案-II实际上会模拟合成网表的行为(此处使用Quartus-II13.1检查)。如果您没有运行步骤"分析和综合"，Quartus会要求您这样做。在再次模拟VWF之前更改VHDL文件时，您必须始终始终手动运行此步骤。合成的网表被写出为Verilog代码，该代码将作为ModelSim仿真器的输入。您可以在文件simulation/qsim/microproj.vo中找到它。

只要Quartus报告警告(或错误)，合成设计的行为就可能与VHDL描述不同。如下所示。要直接模拟您的VHDL描述的行为，您必须编写一个测试台。

下面的测试台将是一个很好的开端。它为前200 ns指定与VWF文件中相同的输入值。您必须在指定位置扩展代码以添加更多信号转换。

library ieee;
use ieee.std_logic_1164.all;

entity microproj_tb is
end entity microproj_tb;

architecture sim of microproj_tb is

  -- component ports
  signal clk      : std_logic := '0';
  signal Sin      : std_logic;
  signal Sout     : std_logic;
  signal cancela  : std_logic;
  signal timerOut : std_logic;

begin  -- architecture sim

  -- component instantiation
  DUT: entity work.microproj
    port map (
      clk      => clk,
      Sin      => Sin,
      Sout     => Sout,
      cancela  => cancela,
      timerOut => timerOut);

  -- clock generation
  clk <= not clk after 10 ns;

  -- waveform generation
  WaveGen : process
  begin
    Sin  <= '0';
    Sout <= '0';
    wait for 40 ns; -- simulation time =  40 ns
    Sin  <= '1';
    wait for 70 ns; -- simulation time =  110 ns
    Sin  <= '0';
    wait for 50 ns; -- simulation time =  160 ns
    Sin  <= '1';

    -- Extend here to add more signal transistions
    wait;
  end process WaveGen;
end architecture sim;

Quartus Prime Lite Edition包括ModelSim Altera Edition的安装。您可以直接在Quartus项目设置中使用ModelSim设置和启动模拟。使用我的测试台对前200 ns的模拟输出如下：

如您所见，输出不同于您对VWF文件的模拟，因为现在模拟的是VHDL设计本身。

---

在您的VHDL代码中，您描述了信号cancela和Ncarros的锁存器，"分析和综合"步骤：

也报告了这一点

Warning (10492): VHDL Process Statement warning at MicroProj.vhdl(26): signal "Ncarros" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at MicroProj.vhdl(27): signal "Ncarros" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at MicroProj.vhdl(48): signal "Ncarros" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at MicroProj.vhdl(21): inferring latch(es) for signal or variable "cancela", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at MicroProj.vhdl(21): inferring latch(es) for signal or variable "Ncarros", which holds its previous value in one or more paths through the process

Info (10041): Inferred latch for "Ncarros[0]" at MicroProj.vhdl(20)
Info (10041): Inferred latch for "Ncarros[1]" at MicroProj.vhdl(20)
Info (10041): Inferred latch for "Ncarros[2]" at MicroProj.vhdl(20)
...
Info (10041): Inferred latch for "Ncarros[31]" at MicroProj.vhdl(20)
Info (10041): Inferred latch for "cancela" at MicroProj.vhdl(20)

在Altera FPGA上，使用逻辑元件(LE)内的查找表(LUT)和组合反馈路径来实现锁存器。在对FPGA编程之后，这种锁存器的状态是未定义的。合成网表的模拟显示为‘X’。

我建议无论如何都要修复闩锁，并将您的代码转换为完全同步的时钟边缘驱动的设计。也就是说，仅在时钟上升沿为cancela和Ncarros分配新值。VHDL代码模式为：

process(clk)
begin
  if rising_edge(clk) then
    -- put all your assignments to cancela and Ncarros here
  end if;
end process;

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