本文介绍了向 Vivado 2014.4 添加库的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我对 Vivado 和 VHDL 还很陌生,我想要一些关于基本问题的指导.

I am quite new to Vivado and VHDL and I would like some guidance on a fundamental issue.

我猜我可以创建自己的库并在我的项目中使用它们,就像我使用默认库和基本库一样

I am guessing that I can create my own libraries and use them in my projects as i do with the default and fundamental ones

例如:

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;

现在,通过在网上浏览,我还没有找到任何具体的答案,没有任何直接的方法可以添加库"(至少在我的 Vivado 版本中).

Now, by browsing on the net, I haven't found anything concrete as an answer, there is not any direct way to "add library" (at least in my version of Vivado).

有没有什么方法可以用类型定义来构建 VHDL 代码,并在您喜欢的任何文件中使用它们,例如在 C 中完成?

Is there any way to build VHDL code with lets say type definitions and use them in any file you like, as it is done in C for example?

推荐答案

所以库只是处理一些名称冲突的一种方法.因此,赛灵思(或其他供应商)可以发布新实体,而不会使其与现有对象发生冲突.您当然也可以这样做,但它实际上并不能为您解决任何问题.

So libraries are just a method for dealing some name clashes. So Xilinx (or another vendor) can release a new entity and not have it clash with your existing objects. You can certainly do that as well, but it doesn't actually solve any problems for you.

相反,您正在寻找的是.让我们看看我们将如何使用它:

Instead, what you are looking for is a package. Let's look at how we would use it:

让我们创建另一个文件 tools.vhd

Let's create another file tools.vhd

package tools is
    type tribool is (true, false, maybe);
end package;

然后我们可以在我们的实体中使用它:

Which we could then use in our entities as:

use work.tools.all;
...
signal x : tribool := maybe;

这篇关于向 Vivado 2014.4 添加库的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持!

06-20 21:05