问题描述
我试图了解perf事件的含义:dTLB加载和dTLB存储?
I'm trying to understand the meaning of the perf events: dTLB-loads and dTLB-stores?
推荐答案
启用虚拟内存后，需要在TLB中查找每个单个内存访问的虚拟地址，以获得相应的物理地址并确定访问权限，并特权(或在无效映射的情况下引发异常). dTLB加载和 dTLB-stores 事件分别表示对数据存储器加载或存储访问的TLB查找.是这些事件的 perf 定义.但是确切的含义取决于微体系结构.
When virtual memory is enabled, the virtual address of every single memory access needs to be looked up in the TLB to obtain the corresponding physical address and determine access permissions and privileges (or raise an exception in case of an invalid mapping). The dTLB-loads and dTLB-stores events represent a TLB lookup for a data memory load or store access, respectively. The is the perf definition of these events. but the exact meaning depends on the microarchitecture.
在Westmere，Skylake，Kaby Lake，Coffee Lake，Cannon Lake(可能还有Ice Lake)上，将 dTLB负载和 dTLB商店映射到MEM_INST_RETIRED.ALL_LOADS 和 MEM_INST_RETIRED.ALL_STORES .在Sandy Bridge，Ivy Bridge，Haswell，Broadwell，Goldmont，Goldmont Plus上，它们分别映射到 MEM_UOP_RETIRED.ALL_LOADS 和 MEM_UOP_RETIRED.ALL_STORES .在Core2，Nehalem，Bonnell和Saltwell上，它们分别映射到 L1D_CACHE_LD.MESI 和 L1D_CACHE_ST.MESI .(请注意，在Bonnell和Saltwell上，事件的正式名称为 L1D_CACHE.LD 和 L1D_CACHE.ST ，以及 perf 使用的事件代码仅在英特尔手册第3卷中有记录，而没有关于性能事件的其他英特尔资料中的记录.)Silvermont和Airmont不支持 dTLB-loads 和 dTLB-stores 事件
On Westmere, Skylake, Kaby Lake, Coffee Lake, Cannon Lake (and probably Ice Lake), dTLB-loads and dTLB-stores are mapped to MEM_INST_RETIRED.ALL_LOADS and MEM_INST_RETIRED.ALL_STORES, respectively. On Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Goldmont, Goldmont Plus, they are mapped to MEM_UOP_RETIRED.ALL_LOADS and MEM_UOP_RETIRED.ALL_STORES, respectively. On Core2, Nehalem, Bonnell, Saltwell, they are mapped to L1D_CACHE_LD.MESI and L1D_CACHE_ST.MESI, respectively. (Note that on Bonnell and Saltwell, the official names of the events are L1D_CACHE.LD and L1D_CACHE.ST and the event codes used by perf are only documented in the Intel manual Volume 3 and not in other Intel sources on performance events.) The dTLB-loads and dTLB-stores events are not supported on Silvermont and Airmont.
在当前所有的AMD处理器上， dTLB负载被映射到 LsDcAccesses ，并且不支持 dTLB-stores .但是， LsDcAccesses 会为加载和存储计数TLB查找.在其他供应商的处理器上，不支持 dTLB加载和 dTLB存储.
On all current AMD processors, dTLB-loads is mapped to LsDcAccesses and dTLB-stores is not supported. However, LsDcAccesses counts TLB lookups for both loads and stores. On processors from other vendors, dTLB-loads and dTLB-stores are not supported.
有关如何映射 perf 核心事件到本地事件.
See Hardware cache events and perf for how to map perf core events to native events.
同一程序在不同微体系结构上的 dTLB-loads 和 dTLB-stores 事件计数可以不同，这不仅是由于微体系结构的差异，还因为其含义事件本身是不同的.因此，即使程序的微体系结构行为在微体系结构上被证明是相同的，事件计数仍然可以不同.可以在此处中找到有关所有英特尔微体系结构上的本机事件的简短说明，以及更详细的信息可以在此处.
The dTLB-loads and dTLB-stores event counts for the same program on different microarchitectures can be different not only because of differences in the microarchitectures but also because the meaning of the events is itself different. Therefore, even if the microarchitectural behavior of the program turned out to be the same on the microarchitectures, the event counts can still be different. A brief description of the native events on all Intel microarchitectures can be found here and a more detailed description on some of the microarchitectures can be found here.
相关:如何解释perf iTLB-loads，iTLB-load-misses .
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