问题描述
当我在Cortex-A9 MPCore中调试MMU时，总是看到域访问控制寄存器，但是，域是什么意思?最多16个域?任何人都可以给我一个链接来解释这个吗?
TL; DR DACR 不仅减少了上下文切换代码路径，而且还可以在上下文切换发生后加快执行速度./p>
有几个链接可以解释域访问控制寄存器或 DACR 的详细信息.例如 ARM的内存访问权限和域 .但是，此页面和许多其他页面并未解释为什么您可能需要此功能.尤其适用于嵌入式应用程序的人们.
以前的ARM功能(ARM体系结构V5)是 PID .使用此功能的原因与 DACR 和域相同. MMU的作用是什么?
- 特权分离-或为某些实体(任务，线程等)提供对内存的访问权限，而其他有限(只读)权限或无访问权限.
- 内存重新映射-虚拟到物理的转换使稀疏/分离的内存变得连续.
- 分页-故障处理程序可以在访问时通过特权较低的代码交换内存.
- 访问行为-MMU可以指定内存是否可缓存，读/写，是否应该缓冲等.
DACR (和 PID )仅与第一个(特权分离)有关.在上下文切换中，操作系统必须管理这种分离.对于大多数MMU(历史上在ARM上)，只有两个特权:用户特权和超级特权.为了容纳多个任务，超级MMU代码必须更改MMU表.这很复杂，因为ARM具有 TLB 和 cache ，它们都具有虚拟地址并依赖于MMU表.
DACR (和 PID )允许通过单次寄存器写入来更改MMU映射.此外， TLB 和 cache 也具有 domain 信息(以及PID的修改地址).这意味着不需要在上下文切换中刷新(并重新填充)这些条目. 域对PID有利，因为可以存在多个访问配置文件.例如，当主任务/线程二进制文件被关闭时，共享库代码可以在上下文切换器上保持可访问性.
将 DACR 与更新MMU表进行比较.
- 至少更改 L1 页表以映射正确的配置文件.
- 清理/使 L1 表和其他无效页表更新(请参见下文).
- 使TLB条目无效(为简单起见，很可能是整件事).
- 使MMU表中的缓存条目无效；可能又是整个事情.
这与更改单个寄存器相对.此外，您可能会使整个缓存和TLB失效.通过 DACR 和简短的上下文切换，代码/数据可以保留在TLB中的缓存和MMU页表条目中.例如，具有检查电子邮件任务和电影播放器的系统.
音频/视频的解码需要占用大量CPU和内存.有时，电子邮件客户端会轮询网络服务器以获取信息.通常没有任何东西.在此短暂的过渡期间，可能只需要一小部分(1-4k)的支票电子邮件代码；一个TLB条目.缓存通常为32k +，因此许多音频/视频缓存和TLB条目可以保持有效.
因此 DACR 不仅减少了上下文切换代码路径，而且还可以在上下文切换发生后加快执行速度.
When I debug MMU in Cortex-A9 MPCore, I always see Domain Access Control Register, but, what does domain means ? up to 16 domains ?Anyone can give me a link to explain this ?
TL;DR The DACR not only decreases the context switch code path, but can also speed execution after the context switch occurs.
There are several links which explain the specifics of Domain Access Control Register or DACR. For example ARM's Memory access permissions and domains. However, this page and many others don't explain why you might need this feature; especially for people use to embedded applications.
A prior ARM feature (ARM architecture V5) was the PID. The reason for this feature is the same as the DACR and domains. What is an MMU used for?
- Privilege separation - or giving some entities (task, thread, etc) access to memory and other limited (read-only) or none.
- Memory remapping - a virtual to physical translation allows sparse/separated memory to become continuous.
- Paging - a fault handler can swap in/out memory on access by less privileged code.
- Access behaviour - the MMU can specify whether memory is cacheable, read/write, should be buffered, etc.
The DACR (and PID) are only concerned with the first (Privilege separation). On a context switch an OS must manage this separation. With most MMUs (historically on the ARM), there are only two privileges being user and super. In order to accommodate multiple tasks, the super MMU code must alter the MMU table. This is complex as the ARM has a TLB and cache, both of which have virtual addresses and depend on the MMU table.
The DACR (and PID) allow the MMU mappings to change with a single register write. Moreover, the TLB and cache also have domain information (and modified address for PID). This means these entries do not need to be flushed (and repopulated) on a context switch. The domains are advantageous to the PID as multiple access profiles can exist. For instance, shared library code may remain accessible on a context switch while the main task/thread binary is switched out.
Compare work with the DACR versus updating the MMU tables.
- Change at least the L1 page tables to map correct profile.
- clean/invalidate the L1 table and others in page table update (see below).
- invalidate the TLB entries (most likely the whole thing for simplicity).
- invalidate the cache entries in MMU table; probably the whole thing again.
This is versus changing a single register. Moreover, you will probably invalidate the entire cache and TLB. With the DACR and a brief context switch, code/data can remain in the cache and MMU page table entries in the TLB. For example, a system with a check email task and a movie player.
The decoding of audio/video is highly CPU and memory intensive. Occasionally, the email client will poll a network server for information. Usually there is nothing. During this brief transition only a small (1-4k) of check email code may be needed; a single TLB entry. Cache is typically 32k+, so much of the audio/video cache and TLB entries can remain valid.
So the DACR not only decreases the context switch code path, but can also speed execution after the context switch occurs.
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