问题描述
在最近的英特尔 ISA 文档中，lfence 指令被定义为序列化指令流(防止其乱序执行).特别是，指令的说明包括这一行:
In recent Intel ISA documents the lfence instruction has been defined as serializing the instruction stream (preventing out-of-order execution across it). In particular, the description of the instruction includes this line:
具体来说，LFENCE 在所有先前的指令在本地完成之前不会执行，并且在 LFENCE 完成之前不会有后续指令开始执行.
请注意，这适用于所有指令，而不仅仅是内存加载指令，使lfence 更多不仅仅是内存排序栅栏.
Note that this applies to all instructions, not just memory load instructions, making lfence more than just a memory ordering fence.
虽然这现在出现在 ISA 文档中，但不清楚它是否是架构的"，即所有 x86 实现都遵守，还是特定于 Intel.特别是，AMD 处理器是否也将 lfence 视为序列化指令流?
Although this now appears in the ISA documentation, it isn't clear if it is "architectural", i.e., to be obeyed by all x86 implementations, or if it is Intel specific. In particular, do AMD processors also treat lfence as serializing the instruction stream?
推荐答案
有一个 MSR 可以配置该行为:
There is an MSR that configures that behaviour:
描述:在处理器中设置一个 MSR，使 LFENCE 是一个调度序列化指令，然后在代码流中使用 LFENCE 来序列化分派(LFENCE 比 RDTSCP 快，后者也是分派序列化).LFENCE 的这种模式可以通过设置 MSR C001_1029[1]=1 来启用.
效果:当 MSR 位置位时遇到 LFENCE，分派将停止，直到 LFENCE指令成为机器中最旧的指令.
Effect: Upon encountering an LFENCE when the MSR bit is set, dispatch will stop until the LFENCE instruction becomes the oldest instruction in the machine.
适用性:所有 AMD 系列 10h/12h/14h/15h/16h/17h 处理器都支持此 MSR.LFENCE 支持是由 CPUID 功能 1 EDX 位 26，SSE2 指示.AMD 系列 0Fh/11h 处理器支持 LFENCE 作为序列化始终但不支持此 MSR.AMD 计划支持此 MSR 并在所有未来访问此位处理器.
Applicability: All AMD family 10h/12h/14h/15h/16h/17h processors support this MSR. LFENCE support is indicated by CPUID function1 EDX bit 26, SSE2. AMD family 0Fh/11h processors support LFENCE as serializing always but do not support this MSR. AMD plans support for this MSR and access to this bit for all future processors.
(来源)
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