问题描述
DMA缓冲区是驱动程序映射的内存.例如，在使用rtl8319的pci-skeleton.c中，我们有:
tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
&tp->tx_bufs_dma);
但是DMA引擎可以驻留在soc或设备中.
**即使设备中装有DMA引擎，是否也应该分配dma缓冲区?为什么 ? **
rtl8139cp数据表(我认为dma是设备的一部分，但对此不确定): http://realtek.info/pdf/rtl8139cp.pdf
我相信"dma引擎"和"dma控制器"指的是同一件事.如果有错，请纠正我.
关于，然
需要明确的是，DMA(直接内存访问)是一种从/向/从主存储器到/从外围设备传输数据的方法.为了方便起见，忽略了内存到内存的DMA和外设到外设的总线主控.
DMA与已编程的I/O(PIO)相反，后者由CPU执行数据传输.对于PIO，CPU将通过查询设备的状态，或者让设备生成中断来通知外设的可用性，以等待外设就绪.轮询的PIO占用大量CPU，并且使用中断的PIO有了巨大的改进.但是，在没有任何CPU干预(设置除外)的情况下执行传输是DMA的含义. DMA传输由系统的DMA控制器(又名第三方DMA)或与外围设备关联的总线主控器(又名第一方DMA)执行. CPU参与(简单，不链接)DMA传输的过程包括设置传输(例如，分配源和目标地址，传输计数)，然后确认传输结束.
不确定您的意思是什么.
分配或获取支持DMA的缓冲区通常不需要映射.
在您的问题中，您暗示具有集成的发送和接收FIFO并使用PCI总线主控的PCI以太网控制器不必映射DMA缓冲区" .以太网控制器是系统的外围设备，它必须从主存储器中获取数据以进行传输，并且通过以太网接收的数据最终必须传输到主存储器中，以便CPU可以对其进行处理.集成的发送和接收FIFO只是存在于主存储器和其余外围设备之间的中间缓冲区.
您的术语太草率了.
SoC是(a)芯片上的系统.典型的SoC当然具有DMA控制器，它是系统的DMA控制器，即用于第三方DMA的控制器.
设备可能具有DMA引擎，尤其是当设备连接的总线支持总线主控时.您引用的以太网控制器确实支持PCI总线主控.该总线主控用于访问(PCI主机的)主存储器.
外围设备可能使用总线主控(而不是系统的DMA控制器)这一事实不能消除对设备驱动程序正确分配可DMA缓冲区的需要.总线主控器具有与系统DMA控制器完全相同的目的:将数据从外设传输到主存储器或从外设传输到主存储器. CPU仅能处理驻留在主存储器中的数据.外设的目的是将数据传输到主存储器进行处理，并从已处理的主存储器传输该数据.
由于总线主控是为了使外设能够以最少的CPU干预访问主存储器，因此所访问的存储器必须具有DMA功能.那就是:
- 存储器必须由总线主控器寻址；
- 内存必须由CPU寻址；
- 必须锁定内存，即不可交换内存；
- 内存必须不可缓存.
当PCI设备驱动程序使用 pci_alloc_consistent()获得用于数据传输的缓冲区时，可以确保使用DMA内存.此例程将返回一个虚拟地址，以供CPU引用此缓冲区，并为dma_handle供总线主设备引用此缓冲区.
DMA buffers are memory mapped by the driver.For example, in pci-skeleton.c, which uses rtl8319 we have:
tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
&tp->tx_bufs_dma);
But DMA engine can reside in soc or in device.
**Is it that dma buffers should be allocated even if DMA engine is in device ? Why ? **
rtl8139cp datasheet (I think the dma is part of the device, but not sure about it):http://realtek.info/pdf/rtl8139cp.pdf
I believe that "dma engine" and "dma controller" refer to the same thing. Please correct me if wrong.
Regards,Ran
To be clear, DMA (Direct Memory Access) is a method to transfer data to/from a peripheral from/to main memory. For convenience memory-to-memory DMA and peripheral-to-peripheral bus-mastering are ignored.
DMA is the opposite of programmed I/O (PIO), where the CPU performs the data transfer. For PIO the CPU would wait for the peripheral to be ready by either polling the device's status, or have the device generate an interrupt to signal the availability of the peripheral.
Polled PIO is CPU intensive, and PIO using interrupts is a huge improvement. But performing the transfer without any CPU involvement (other than the setup) is the meaning of DMA. The DMA transfer is performed by either the system's DMA controller (aka third-party DMA) or a bus master associated with the peripheral (aka first-party DMA). The CPU's involvement in a (simple, not chained) DMA transfer consists of setting up the transfer (e.g. assign source & destination addresses, transfer count), and then acknowledge the end of the transfer.
Not sure what you mean by this.
Allocating or acquiring a DMA-able buffer does not typically require mapping.
In your question you insinuate that a PCI Ethernet controller that has integrated transmit and receive FIFOs and uses PCI bus mastering does not have to "map DMA buffers". The Ethernet controller is a peripheral of the system, and it has to get data from main memory to transmit, and the data it receives over Ethernet has to be eventually transferred to main memory so that the CPU can process it.The integrated transmit and receive FIFOs are merely intermediate buffers that exist in between main memory and the rest of the peripheral.
You're sloppy with terminology.
A SoC is a System on (a) Chip. The typical SoC will certainly have a DMA controller, and it is the system's DMA controller, i.e. for third-party DMA.
A device might have a DMA engine, especially if the bus it connects to supports bus mastering. The Ethernet controller you cite does support PCI bus mastering. This bus mastering is to access main memory (of the PCI host).
The fact that a peripheral might use bus mastering (instead of the system's DMA controller) cannot negate the need to properly allocate a DMA-able buffer by the device driver. The bus master has the exact same purpose of the system's DMA controller: to transfer data from/to the peripheral to/from main memory. The CPU can only process data that resides in main memory. The purpose of peripherals is to transfer that data to main memory for processing, and to transfer that data from main memory that has been processed.
Since bus mastering is for enabling a peripheral to access main memory with minimal CPU intervention, that memory which is accessed has to be DMA-able. That is:
- the memory has to be addressable by the bus master;
- the memory has to be addressable by the CPU;
- the memory has to be locked down, i.e. not swappable;
- the memory has to be non-cacheable.
When a PCI device driver uses pci_alloc_consistent() to obtain a buffer for a data transfer, it is assured of DMA-able memory. This routine will return a virtual address for the CPU to reference this buffer, and a dma_handle for the bus master to reference this buffer.
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