问题描述
我的理解是当NIC适配器接收到新数据包时，上半部分处理程序使用DMA将数据从RX缓冲区复制到主存储器。我认为这个处理程序不应该在传输完成之前退出或释放INT引脚，否则新的数据包会破坏旧的数据包。
My understanding is that when a NIC adapter receives new packets, the top half handler uses DMA to copy data from the RX buffer to the main memory. I think this handler should not exit or release the INT pin before the transmission is completed, otherwise new packets would corrupt the old ones.
但是，DMA通常被认为是异步的本身需要中断机制来通知CPU数据传输完成。因此我的问题是，DMA实际上是同步的，或者中断实际上可能发生在另一个中断处理程序中？
However, DMA is generally considered asynchronous and itself requires the interrupt mechanism to notify the CPU that data transmission is done. Thus my question, is DMA actually synchronous here, or interrupt can in fact happen within another interrupt handler?
推荐答案
一般来说，这个通过NIC（设备驱动程序）和主机CPU之间的环描述符进行同步。您将获得的数据包路径详细信息。我已经解释了下面的环描述符。
In general, this synchronisation happens via ring descriptor between NIC(device driver) and host CPU. You will get packet path details here. I have explained the ring-descriptors below.
编辑：
让我用。如果你看一下3.2.3节，其中给出了 RX描述符格式 ，它有 状态 字段，解决了数据包所有权问题。对于谁拥有数据包（NIC驱动程序或CPU），有两个要点可以避免争用和数据包损坏。
Let me explain with Intel's ethernet Controller. If you look at section 3.2.3, where the RX descriptor format is given, it has status field which solves packet ownership problem. There are two major points to avoid contention and packet corruption as to who owns the packet (NIC driver or CPU).
DMA（从I / O设备到主机内存）： RX / TX环由'硬件描述符'和'缓冲区'组成（雕刻）来自主机内存）。当我们说DMA，控制器传输数据时，这会从硬件FIFO发送到这个主机内存。
DMA (from I/O device to Host memory): RX/TX Ring consists of 'hardware descriptors' and 'buffers' (carved from host memory). When we say DMA, controller transfer data, this happens from hardware FIFOs to this host memory.
- 让我们假设我的环缓冲区（512） （字节）不足以容纳完整的传入数据包（1500或Jumbo数据包），在这种情况下，数据包可能跨越多个环形缓冲区并且 EOP（数据包结束） status字段，表示现在已收到完整的数据包（考虑到已完成所有健全性检查/校验和）。
- 其次是谁拥有该数据包（驱动程序或CPU以供进一步消费）？现在，直到状态标志DD（Descriptor Done）被设置，它才属于驱动程序。一旦设置，CPU就可以抓住它进行拣选。
这是特定于RX路径的。 TX路径略有不同。
This is specific to RX path. TX path is slightly different.
这样考虑，系统中一直有多个中断（IO，键盘，鼠标等）发生，但两次中断之间的持续时间是这样的CPU可以在其间做很多其他好事。为了进一步卸载CPU工作，DMA有助于传输数据。因此，如果引发中断并调用子程序，则所有后续中断都可以被屏蔽，因为您已经在该子程序中，但请相信我这些子程序非常小，它们几乎不会消耗，直到您的下一个数据包到达为止。这意味着您的数据包到达速度必须高于您的处理速度。
Consider it this way, there are multiple interrupts (IO, keyboard, mouse, etc) happening all the time in the system, but the time duration between two interrupts are so huge that CPU can do lot of other good stuff in between. And to further offload CPUs work DMA helps transferring data. So if an interrupt is raised and subroutine is called, all the subsequent interrupts can be masked as you are already inside that subroutine, but trust me these subroutine are very tiny they hardly consume any time until your next packet arrives. That means your packet arriving speed has to be higher than your processing speed.
另一个例子：对于路由器/交换机99％的时间任务是路由和切换因此子程序和中断优先级它们是完全不同的，而且它们总是被大量数据包轰炸，因此在这种情况下子程序永远不会到来，直到有另一个数据包在海湾。至少我已经研究过这种网络设备。
Another Ex: for router/switches 99% time task is routing and switching hence subroutine and interrupt priorities are completely different, moreover all the time they are bombard with tons of packets and hence the subroutine in such cases will never come until there is another packet at bay. At least i have worked on such networking gears.
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