问题描述
我想创建Verilog内的阵列中，将包含的值 X ，是给定的功能。所以数组中的每个内容将包含 X 的价值和是的值。因此，可以说，我有以下值（X，Y）
（3,2）
（5,10）
（1,5）
最后一个数组将是这个样子：
表[I] [X] [Y]表[0] [3] [2]
表[1] [5] [10]
表[2] [1] [5]
是否有可能使这个阵列中的Verilog和综合是？如果是这样，我怎么能访问每一个点在这个阵列上？
我认为你要得到的是一个数组元素在其中可以容纳两个数字。他们这样，你有presented很是怪异。你与你的榜样code说的是，你有一个三维数组，其中有些元素与特定值 I ， X 和是，将有一个值，但没有指定什么样的价值。
你在文字说的是，你想要的 I 元素，每个元素将有两个值的表：一个是 X 和一个是。那是后话，我们可以工作了，但不是与您提供的实现（三维数组）。
这就是说，你必须首先考虑如何为你的的性质X ，是值要存储在表中。 Verilog的最好工作，整数，所以我会假设。你还需要知道你的整数将会有多少位使用。比方说，他们将使用8位，所以有效的 X ，是值的范围是 [-128，+ 127] 的符号考虑。
现在，你必须知道你要多少 X ，是对你的表来存储。比方说，这是 N 值，其中 N 是某种参数对您的模块。
然后，将表将被实例是这样的：
REG [15：0]表[0..N-1];
因此，表[I] [7：0] 可以容纳一个8位的值，例如，是和表[I] [15：8] 可以持有另外8位值，比如 X
要初始化这个表，在一个综合的方式，最常用的方法是复位信号添加到您的模块，并使用它来初始化表的内容，如：
REG [15：0]表[0..N-1];
整数i;
总是@（posedge时钟）开始
如果（复位== 1'b1的）开始
表[0]＆LT; = {8'd3，8'd2};
表[1] = {8'd5，8'd10};
表[2]＆LT; = {8'd1，8'd5};
为（ⅰ= 3; I＆下; N; I = I + 1）//初始化表的其余部分为0,0
表[1] - = {8'd0，8'd0};
结束
否则......
结束
要在位置访问点 I ，您只需使用：
表[I] [15：8] X值
表[I] [7：0] Y值
如果打靶一个Xilinx器件，还可以初始化寄存器的内容，无论是在分布式RAM或块RAM，使用初始块
REG [15：0]表[0..N-1];
整数i;
最初的开始
表[0] = {8'd3，8'd2};
表[1] = {8'd5，8'd10};
表[2] = {8'd1，8'd5};
为（ⅰ= 3; I＆下; N; I = I + 1）//初始化表的其余部分为0,0
表[i] = {8'd0，8'd0};
结束
I want to create an array in Verilog which is going to contain the values x, y of a given function. So each content of the array is going to contain a value of x and a value of y. So lets say that I have the following values for (x,y)
(3,2)
(5,10)
(1,5)
The final array will look something like this:
Table[i][x][y]
Table[0][3][2]
Table[1][5][10]
Table[2][1][5]
Is it possible to make this array in Verilog and be synthesizable? If so, how can I access each point on this array?
I think that what you want to get is an array in which an element can hold two numbers. They way you have presented it is weird. What you say with your example code is that you have a tri-dimensional array, in which some elements with certain values for i,x and y, will have a value, but you don't specify what value.
What you say in the text is that you want a table of i elements, in which each element will have two values: one for x and one for y. That is something that we can work out, but not with the implementation (the tri-dimensional array) you provide.
That said, you must first consider how is the nature of your x,y values you want to store in the table. Verilog work best with integers, so I will assume that. You also need to know how many bits your integers will use. Let's say they will use 8 bits, so valid x,y values are in the range [-128,+127] is sign is considered.
Now you must know how many x,y pairs you want to store in your table. Let's say it's N values, where N is some kind of parameter to your module.
Then, the table would be instantiated like this:
reg [15:0] Table[0..N-1];
So, Table[i][7:0] can hold one 8 bit value, for example, y, and Table[i][15:8] can hold another 8 bit value, say x.
To initialize this Table, in a synthesizable way, the most common method is to add a reset signal to your module and use it to initialize Table contents, like this:
reg [15:0] Table[0..N-1];
integer i;
always @(posedge clk) begin
if (reset == 1'b1) begin
Table[0] <= {8'd3, 8'd2};
Table[1] <= {8'd5, 8'd10};
Table[2] <= {8'd1, 8'd5};
for (i=3;i<N;i=i+1) // initialize the rest of Table to 0,0
Table[i] <= {8'd0, 8'd0};
end
else ......
end
To access the point at location i, you simply use:
Table[i][15:8] for X value
Table[i][7:0] for Y value
If targetting a Xilinx device, you can also initialize contents of a register, be it in distributed RAM or block RAM, using an initial block
reg [15:0] Table[0..N-1];
integer i;
initial begin
Table[0] = {8'd3, 8'd2};
Table[1] = {8'd5, 8'd10};
Table[2] = {8'd1, 8'd5};
for (i=3;i<N;i=i+1) // initialize the rest of Table to 0,0
Table[i] = {8'd0, 8'd0};
end
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