问题描述
我找到了一种方法来读取L1（数据和指令）高速缓存使用的。我想读L2性能计数器了。有没有谁知道如何测量L2高速缓存的命中率可能与ARM汇编或更高的水平，如Java？
I found a way to read L1(data and instruction) cache using http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4237.html.I want to read L2 performance counters too. Is there anyone who knows how to measure L2 cache hit rate possibly with ARM assembly or in higher level like Java?
推荐答案
访问性能数据L2依赖的L2-控制器上。我不知道有多少不同的人也有，但当前A9平台PL310是pretty的共同和功能事件计数器，可捕捉请求和命中（http://infocenter.arm.com/help/index。 JSP？主题= / com.arm.doc.ddi0246a / index.html的）。虽然访问这些计数器可能是困难的。如果幸运的话，内核可能会提供一个接口，这些寄存器，但很可能不是，他们不是从用户空间访问。在这种情况下，你必须找到存储器映射平台，并编写内核模块或类似的东西。
Accessing performance data for the L2 is dependent on the L2-controller. I don't know how many different ones there are, but for current A9 platforms the PL310 is pretty common and features event counters which can capture requests and hits (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/index.html ). Though accessing those counters might be difficult.If you're lucky the kernel might offer an interface to those registers, but it's likely that not and that they aren't accessible from user space. In that case you would have to find the memory map for your platform and write a kernel module or something like that.
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