如何实现(伪)硬件随机数生成器

问题描述

如何在HDL(verilog)中实现硬件随机数生成器?

How do you implement a hardware random number generator in an HDL (verilog)?

需要考虑哪些选项?

此问题遵循 self-answer 格式.鼓励添加答案和更新.

This question is following the self-answer format. Addition answers and updates are encouraged.

推荐答案

通常 LFSR 呼叫的第一个港口.实现是相对简单的，将具有多个项XORd的移位寄存器一起创建反馈项.

An LFSR is often the first port of call. Implementation is relatively simple, a shift register with a number of terms XORd together to create the feedback term.

在考虑实施LFSR时，需要考虑随机数的位宽和数字的可重复性.使用N位，最大LFSR将具有(2**N) - 1状态.全零状态不能在没有其他硬件的情况下使用.

When considering the implementation of the LFSR, the bit width of the random number and the repeatability of the number need to be considered. With N bits a Maximal LFSR will have (2**N) - 1 states. All zero state can not be used with out additional hardware.

一个示例4位LFSR ，其位为0和位4:

An example 4 bit LFSR with taps a bit 0 and bit 4:

module fibonacci_lfsr(
  input  clk,
  input  rst_n,

  output [4:0] data
);

wire feedback = data[4] ^ data[1] ;

always @(posedge clk or negedge rst_n)
  if (~rst_n)
    data <= 4'hf;
  else
    data <= {data[3:0], feedback} ;

endmodule

可以从下面的表.

例如，一个17,820,000，宽30位的序列可以使用:的抽头.

For example a sequence of 17,820,000, 30 bits wide could use taps of :

0x20000029 => bits "100000000000000000000000101001"
0x2000005E => bits "100000000000000000000001011110"
0x20000089 => bits "100000000000000000000010001001"

第一个反馈项为:

feedback = data[29] ^ data[5] ^ data[3] ^ data[0];

如果不确定抽头的顺序，请记住，MSB始终是反馈点.最后一个(抽头)反馈点定义了LFSR的有效长度，之后它只是一个移位寄存器，与反馈序列无关.

If you are unsure of the order of the taps, remember that the MSB will always be a feedback point. The Last (tap) feedback point defines the effective length of the LFSR, after that it would just be a shift register and have no bearing on the feedback sequence.

如果需要一个69,273,666的序列，则必须实现31位LFSR，并为您的随机数选择30位.

If you needed a sequence of 69,273,666 you would have to implement a 31 bit LFSR and choose 30 bits for your random number.

LFSR是创建1位随机数流的一种好方法，但是，如果您连续获取多个位，则值之间存在相关性，那就是相同的数字移位和抖动位.如果该数字被用作抖动流，则可能要引入一个映射层，例如，每隔一位交换一次.或者，对每个位使用不同长度或抽头点的LFSR.

LFSRs are a great way to create a 1-bit random number stream but if you are taking multiple consecutive bits that there is a correlation between values, it is the same number shifted plus dither bit. If the number is being used as a dither stream you may want to introduce a mapping layer, for example swap every other bit. Alternatively use an LFSR of different length or tap points for each bit.

高效移位寄存器，LFSR计数器和长伪随机序列生成器，
Peter Alfke的Xilinx应用笔记.

Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators,
A Xilinx app note by Peter Alfke.

Virtex器件中的线性反馈移位寄存器，
Maria George和Peter Alfke撰写的Xilinx应用笔记.

Linear Feedback Shift Registers in Virtex Devices,
A Xilinx app note by Maria George and Peter Alfke.

这篇关于如何实现(伪)硬件随机数生成器的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！