什么是推断的闩锁以及在 if 条件中缺少 else 语句时如何创建它.有人能简单解释一下吗?

本文介绍了什么是推断的闩锁以及在 if 条件中缺少 else 语句时如何创建它.有人能简单解释一下吗?的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！

问题描述

我试图找出推断的闩锁以及为什么内部需要它，但我找不到任何足够详细的资源.

I tried to figure out the inferred latch and why it is needed internally, but I couldn't find any resources with enough detail.

推荐答案

在未将网络分配给已知值的组合块中推断出锁存器.为自己分配一个网络仍然会推断出一个锁存器.锁存器也可以通过丢失的信号来推断，形成一个灵敏度列表和反馈回路.

A latch is inferred within a combinatorial block where the net is not assigned to a known value. Assign a net to itself will still infer a latch. Latches can also be inferred by missing signals form a sensitivity list and feedback loops.

在 Verilog/SystemVerilog 中推断预期锁存器的正确方法是:

The proper way of inferring a intended latch in Verilog/SystemVerilog are:

/* Verilog */       ////    /* SystemVerilog */
always @*           ////    always_latch
begin               ////    begin
  if (en) q = d;    ////      if (en) q = d;
end                 ////    end

意外推断闩锁的方式:

敏感度列表缺少信号(这就是应该使用 @* 的原因):

always @(a or b) // inferred latch :: "c" missing for the sensitivity list.
begin
  out = a + b + c;
end

缺少条件:

Missing Condition:

always @*
begin
  case(in[1:0])
   2'b00:  out = 1'b0;
   2'b01:  out = 1'b1;
   2'b10:  out = 1'b1;
   // inferred latch "out" :: missing condition 2'b11/default
 endcase
end
always @*
begin
  next0 = flop0;
  next1 = flop1;
  // inferred latch "next2" :: missing initial condition
  next3 = flop3;
  case(a[2:0])
   3'b001:             next0 = in;
   3'b010:  if(b)      next1 = in;
   3'b100:  if(c)      next2 = in;
   default: if(!b&&!c) next3 = in;
 endcase   
end

反馈循环:
Feedback Loop:
```
assign out = en ? in : out; // inferred latch "out" :: feedback to mux
assign a = en ? z : c;
// ... any amount of code between ...
assign z = en ? a : y; // inferred latch "a" :: feedback chain
```
- 反馈循环可以遍历层次结构和设计.