在Emacs Verilog模式下对齐代码？

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问题描述

我习惯在emacs中用VHDL编写代码，该代码具有很好的美化功能，可以对齐信号分配。 Verilog模式是否有类似功能？

I'm used to writing code in VHDL in emacs, which has the nice beautify functionality that will align signal assignments. Is there something similar with the Verilog Mode?

转换为：

r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

为此：

r_Tx_Done     <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main   <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

Verilog模式在保持效果很好 else 开始 end 对齐，但它没有像我想要的那样对齐作业。请注意，if语句内部与if语句外部的< = 不对齐。本质上，我希望每个开始/结束块都单独处理。

Verilog mode does a good job keeping if else begin end aligned, but it doesn't align assignments like I want. Note that inside the if statement doesn't align to <= outside the if statement. Essentially I want each begin/end block treated separately.

`推荐答案`

基于，您可以尝试自定义 align-rules-list 。

Based on this answer you can try to customize align-rules-list.

类似这样的方法应该有所帮助：

Something like this should help:

(eval-after-load "align"
  '(add-to-list 'align-rules-list
                '(verilog-assignment
                  (regexp . "\\(\\s-*\\)<=")
                  (mode   . '(verilog-mode))
                  (repeat . nil))))

现在 Mx align 应该应用新的对齐规则。

Now M-x align should apply the new alignment rule.

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