本文介绍了在 VHDL 测试平台中读取文本文件的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!
问题描述
我有一个文件 source.txt
,它看起来像这样:
I have a file source.txt
, it looks like this:
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
00660066006700670067006800680069006B006D006E
0065006500660067006700690069006A006B006C006E
00650065006600670067006700680069006A006C006D
00650065006600670067006600660068006A006B006D
006500650066006700670065006600670069006B006D
00650065006600670067006600670068006A006C006D
0065006500660067006700690069006A006B006C006E
*
每一行后面都有一个隐藏的换行符'\n'.星号*"是我可见的文件结尾字符.
After each line there is the hidden newline character '\n'.The asterix '*' is my visible end-of-file character.
我如何在 VHDL 中编写一个测试平台来执行以下操作:
How do I write a testbench in VHDL that does the following:
- 读取文件
- 在向量中存储一行
- 将该向量写入新的
target.txt
推荐答案
使用 VHDL-2008,并显示正在进行的 std_logic_vector
,代码可以是:
Using VHDL-2008, and showing the std_logic_vector
underway, the code can be:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity tb is
end entity;
architecture syn of tb is
begin
process is
variable line_v : line;
file read_file : text;
file write_file : text;
variable slv_v : std_logic_vector(44 * 4 - 1 downto 0);
begin
file_open(read_file, "source.txt", read_mode);
file_open(write_file, "target.txt", write_mode);
while not endfile(read_file) loop
readline(read_file, line_v);
hread(line_v, slv_v);
report "slv_v: " & to_hstring(slv_v);
hwrite(line_v, slv_v);
writeline(write_file, line_v);
end loop;
file_close(read_file);
file_close(write_file);
wait;
end process;
end architecture;
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