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问题描述

  • 在verilog中,我可以为矢量分配字符串,例如:

  • In verilog, I can assign a string to a vector like:

wire [39:0] hello;
assign hello = "hello"; 

  • 在VHDL中,我很难找到这样的方法:

  • In VHDL, I'm having difficulty finding a method like this:

    SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0);
    ...
    hello <= "hello";
    

  • 我一直在使用:

    hello <= X"65_68_6c_6c_6f";
    

    不清楚,对于大型字符串来说很费时间.

    which is unclear and time consuming for large strings.

    我查看了 textio txt_util,但似乎都不太清楚解释字符串并将其转换为std_logic.

    I've looked at the textio package and thetxt_util package, but neither seem to be very clear on how to interpret a string and convert it to std_logic.

    在VHDL中是否有一种简单的方法将ascii代码分配给std_logic?

    Is there a simple method of assigning ascii codes to std_logic in VHDL?

    这是一个最小的例子:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    
    ENTITY test IS
    PORT(
       ctrl : IN std_logic;
       stdout : OUT std_logic_vector (39 DOWNTO 0)
    );
    END ENTITY;
    
    ARCHITECTURE rtl OF test IS
       SIGNAL temp : std_logic_vector (39 DOWNTO 0);
    BEGIN
       stdout <= temp;
       PROCESS(ctrl)
       BEGIN
          IF (ctrl = '0') THEN
             temp <= "hello"; -- X"68_65_6C_6C_6F";
          ELSE
             temp <= "world";
          END IF;
       END PROCESS;
    
    END rtl;
    

    推荐答案

    此选项对于Morten的回答几乎没有变化-它只使用一个乘法,它复制字符串而不是创建别名,它使用一个附加变量,并返回一个具有递增索引范围的标准逻辑向量.

    This one varies little for Morten's answer - it only uses one multiply, it copies the string instead of creating an alias, it uses an additional variable and it returns a standard logic vector with an ascending index range.

    从名为string_utils的程序包中:

    From a package called string_utils:

    library ieee; 
    use ieee.numeric_std.all;
    -- ...
        function to_slv(s: string) return std_logic_vector is 
            constant ss: string(1 to s'length) := s; 
            variable answer: std_logic_vector(1 to 8 * s'length); 
            variable p: integer; 
            variable c: integer; 
        begin 
            for i in ss'range loop
                p := 8 * i;
                c := character'pos(ss(i));
                answer(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); 
            end loop; 
            return answer; 
        end function; 
    

    您可以添加一个带有默认值的参数,该参数指定返回值的升/降索引范围.您只需要提供非默认参数即可.

    You could add an argument with a default specifying ascending/descending index range for the return value. You'd only need to provided the argument for the non default.

    这篇关于VHDL:是否有方便的方法将ascii值分配给std_logic_vector?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持!

    09-18 23:43