问题描述
快速的问题，事先假设
mov eax, 0
这是更有效？
inc eax
inc eax
或
add eax, 2
此外，如果两个 INC 是速度更快，做编译器（比方说，GCC）通用（即W / O积极的优化标志）优化 VAR + = 2 呢？
Also, in case the two incs are faster, do compilers (say, the GCC) commonly (i.e. w/o aggressive optimization flags) optimize var += 2 to it?
感谢您的时间！
PS：不要打扰与不prematurely优化的变化来回答，这仅仅是学术兴趣
PS: Don't bother to answer with a variation of "don't prematurely optimize", this is merely academic interest.
推荐答案
在同一个寄存器中的两个 INC 指令（或更一般地说两个读 - 修改 - 写指令）别总是具有至少两个周期的依赖关系链。这是假设一个时钟延迟的增量，这是因为486.也就是说，如果周边指示不能与两个增量的指令来隐藏那些延迟，所述code将执行慢。进行交错的情况下
Two inc instructions on the same register (or more generally speaking two read-modify-write instructions) do always have a dependency chain of at least two cycles. This is assuming a one clock latency for a inc, which is the case since the 486. That means if the surrounding instructions can't be interleaved with the two inc instructions to hide those latencies, the code will execute slower.
但是，没有编译器会发出你提出反正指令序列（ MOV EAX，0 将 XOR EAX，EAX ，见）
But no compiler will emit the instruction sequence you propose anyway (mov eax,0 will be replaced by xor eax,eax, see Any reason to do a "xor eax, eax"?)
mov eax,0
inc eax
inc eax
将被optimizied到
it will be optimizied to
mov eax,2
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