七段显示输出未知

本文介绍了七段显示输出未知的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！

问题描述

我正在尝试制作一个从0到9的计数器，并显示在我的Nexys A7的七段显示器上.代码可以编译，但是在测试台中它表明所有输出都是未知的.我测试了我的时钟分频器模块，看起来不错.我不确定为什么它不起作用.

I'm trying to make a counter that counts from 0-9 and displays on my Nexys A7's seven segment display. The code compiles, but in the testbench it shows that all the outputs are unknown. I tested my clock divider module, and it looks fine. I'm not sure why it isn't working.

module BCD_sevenseg(
    input clk,
    output segA, segB, segC, segD, segE, segF, segG, segDP, div_clk
    );

    counter module1(
    .clk(clk),
    .div_clk(div_clk)
    );

    reg[3:0] BCD; //BCD signal is 4 bits wide
    always@(posedge clk) //check every positive edge
        if(div_clk) //executes if counter value from module1 is true
            BCD <= (BCD == 4'h9 ? //check if BCD is at binary 9
            4'h0 : BCD + 4'h1 );
            //true: reset to 0
            //false: count up

    reg [7:0] sevenseg; //8 segments on 7 segment display (w/ decimal point)
    always@(*)
    case(BCD) //one case for each digit
        4'h0: sevenseg = 8'b11111100;
        4'h1: sevenseg = 8'b01100000;
        4'h2: sevenseg = 8'b11011010;
        4'h3: sevenseg = 8'b11110010;
        4'h4: sevenseg = 8'b01100110;
        4'h5: sevenseg = 8'b10110110;
        4'h6: sevenseg = 8'b10111110;
        4'h7: sevenseg = 8'b11100000;
        4'h8: sevenseg = 8'b11111110;
        4'h9: sevenseg = 8'b11110110;
        default: sevenseg = 8'b00000000;
    endcase

    assign {segA, segB, segC, segD, segE, segF, segG, segDP} = sevenseg;

endmodule

时钟分频器:

module counter(
    input clk,
    output reg div_clk=0
    );

integer count_value=0;

always@(posedge clk)
begin
    if(count_value == 10)//change this number to adjust output signal frequency
    begin
        div_clk = ~div_clk;
        count_value <= 0;
    end
    else
        count_value <= count_value+1;
end


endmodule

测试平台代码:

module BCD_sevenseg_tb();

reg clk=0;
wire segA, segB, segC, segD, segE, segF, segG, segDP, div_clk;


BCD_sevenseg UUT(
.clk(clk),
.segA(segA),
.segB(segB),
.segC(segC),
.segD(segD),
.segE(segE),
.segF(segF),
.segG(segG),
.segDP(segDP),
.div_clk(div_clk)
);

always
#1 clk=~clk;

endmodule

推荐答案

您的输出始终为X，因为 BCD 始终为X.您将 BCD 声明为reg ，默认值为X.您需要将 BCD 初始化为一个已知值，例如0.

Your outputs are always X because BCD is always X. You declared BCD as a reg, which defaults to X. You need to initialize BCD to a known value, such as 0.

出于仿真目的，您可以使用以下方法轻松完成此操作:

For simulation purposes, you can do this simply with:

reg[3:0] BCD = 0; //BCD signal is 4 bits wide

初始化信号的标准方法是使用复位输入信号.例如:

A standard way to initialize signals is to use a reset input signal. For example:

always @(posedge clk) begin
    if (reset) begin
        BCD <= 4'h0;
    end else begin
        if (div_clk) BCD <= (BCD == 4'h9 ? 4'h0 : BCD + 4'h1 );
    end
end

这篇关于七段显示输出未知的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！

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