问题描述
我正在 Verilog 中为我正在为计算机体系结构创建的处理器开发一个简单的符号扩展器.
I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture.
这是我到目前为止所得到的:
Here's what I've got so far:
`timescale 1ns / 1ps
module SignExtender( CLK, extend, extended );
input[7:0] extend;
input CLK;
output[15:0] extended;
reg[15:0] extended;
wire[7:0] extend;
always
begin
while (CLK == 1)
extended[7:0] = extend[7:0];
extended[15:8] = {8{extend[7]}};
end
endmodule
我添加了 while (CLK == 1) 认为可以解决我的问题,我认为这是一个无限循环.当我尝试在 iSim 中测试时,电路从未初始化.
I added the while (CLK == 1) thinking that would solve my problem, which I believe is an infinite loop. When I try to test this in iSim, the circuit never initializes.
我也尝试删除复制语法,只对 [8]-[15] 执行扩展 [8] = 扩展 [7] 等,但出现相同的结果,所以我很确定最内层的语法是正确.
I also tried removing the copying syntax and just doing extended[8] = extend[7] etc. for [8]-[15], but the same result occurs, so I'm pretty sure that the innermost syntax is correct.
这是测试文件:
`timescale 1ns / 1ps
module SignExtender_testbench0;
// Inputs
reg [7:0] extend;
reg CLK;
// Outputs
wire [15:0] extended;
// Instantiate the Unit Under Test (UUT)
SignExtender uut (
.extend(extend),
.extended(extended)
);
initial begin
// Initialize Inputs
extend = 0;
#100; // Wait 100 ns for global reset to finish
extend = -30;
CLK = 1;
#10;
CLK = 0;
if (extended == -30)
$display("okay 1");
else
$display("fail 1");
extend = 40;
#10;
if (extended == 40)
$display("okay 2");
else
$display("fail 2");
end
endmodule
有什么想法可以让我成功地做到这一点吗?
Any ideas how I can do this successfully?
推荐答案
你差点就搞定了...
always @( posedge clk ) begin
extended[15:0] <= { {8{extend[7]}}, extend[7:0] };
end
您还缺少40"测试的时钟边沿.试试这个,&让我知道你的进展如何...
You're also missing a clock edge for the '40' test. Try this, & let me know how you get on...
这篇关于如何在 Verilog 中对数字进行符号扩展的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持!