问题描述
在 VHDL 中，创建信号或向量时是否需要初始化?如果忘记初始化信号或整数值会发生什么?
In VHDL, is initialization necessary when creating a signal or a vector?What happens if one forgets to initialize a signal or integer value?
推荐答案
在模拟中，如果你不设置一个初始值，你的vector的每个元素都会得到默认 值(这是由 VHDL 语言规范定义的).对于枚举类型，这是枚举类型中定义的第一个元素:布尔值将是 false，std_logic 将是 'U'(未定义).请注意，U"在电路中没有意义.这只是对验证工程师的一个提示，即您不知道触发器在上电时的值.
In simulation, if you do not set an initial value, each element of your vector will get the default value (this is defined by the VHDL language specification). For enum types, this is the first element defined in the enumeration type: booleans will be false, std_logic will be 'U' (undefined). Note that 'U' has no meaning in electrical circuits. It is merely a hint for the verification engineer that you don't know which value the flip-flop has at power-on.
综合后:FPGA 综合器将使用您设置的初始值作为触发器和存储器的开机"值如果目标技术支持此值！如果该技术不支持强制初始值(对于 ASIC)，则开机时的初始值未知.它可以是 1 或 0.(参见例如:http://quartushelp.altera.com/11.0/mergedProjects/hdl/vhdl/vhdl_pro_power_up_state.htm)
After synthesis: FPGA synthesizers will use the initial value that you set as the "power on" value of the flip-flops and memories if the target technology supports this! If the technology does not support a forced initial value (and for ASICs), the initial value at power-on is not known. It could be 1 or 0. (See for example: http://quartushelp.altera.com/11.0/mergedProjects/hdl/vhdl/vhdl_pro_power_up_state.htm)
两种可能的样式:
- 选择一个明确的初始值，有或没有明确的复位电路(通常用于现代 FPGA)
- 设置'U'为初始值，并有合适的复位电路来强制一个已知的复位值
如果你选择第一种，一定要检查你的目标技术是否支持这种风格！
If you go with the first choice, be sure to check if your target technology supports this style!
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