问题描述
简单的问题
如果我需要使用 4 个 8 位数字,我会声明以下 reg.
If I need to use 4 8-bit numbers, I would declare the following reg.
reg [7:0] numbers [3:0]
我对第一个和第二个声明([7:0] 和 [3:0])之间的区别感到很困惑.他们应该按什么顺序来?第一个保留数字的大小,而第二个保留数字的数量,反之亦然?是 [7:0] 还是 [0:7] 给出正确的顺序?
I'm quite confused about the difference between the first and second declaration ([7:0] and [3:0]). In what order should they come? Does first one stay for the size of a number while the second is for the number of numbers or vice versa? And is [7:0] or [0:7] give the right order?
提前致谢.
普通的数字数组看起来像这样,例如
Ordinary arrays of numbers look like this, for example
0000
0110
0001
共有三个 4 位数字(0000、0110、0001).我们可以通过使用数组索引来访问它们.因此,访问第二个数字的第一位数字是通过这样的方式完成的
There are three 4-bit numbers (0000, 0110, 0001). We can access them by using array indices. So, accessing the first digit of the second number is done by something like this
a[0][1]
假设这个数组存储在一个变量a中.
assuming that this array is stored in a variable a.
回到 Verilog,例如,如果我交换 reg 中的值或以相反的顺序 ([0:7]) 声明它们,访问元素会如何变化?
Returning to Verilog, how would accessing elements change if I would swap values in reg or declare them in reverse order ([0:7]), for example?
推荐答案
reg[7:0]
是一个 8 位的寄存器",或变量reg[7:0] numbers[3:0]
是一个具有 4 个元素的一维数组,命名为numbers
,每一个都是一个 8 位寄存器numbers
的元素被访问为numbers[index]
numbers[i][j]
是numbers[i]
的位选择.它访问位j
在numbers
的 - 正如工具所说,数组索引更传统编号
[lsb:msb]
,但没有充分的理由这样做.
i
th 个元素中reg[7:0]
is an 8-bit "register", or variablereg[7:0] numbers[3:0]
is a 1-D array with 4 elements, namednumbers
, each of which is an 8-bit register- An element of
numbers
is accessed asnumbers[index]
numbers[i][j]
is a bit-select ofnumbers[i]
. It accesses bitj
in thei
th element ofnumbers
- As toolic says, it's more conventional for array indices to benumbered
[lsb:msb]
, but there's no good reason for this.
当分配两个对象时,位从左到右复制,对于 VHDL.
When assigning two objects, bits are copied left-to-right, as for VHDL.
Verilog 对位和部分选择以及数组索引的检查(非常)很差.请参阅下面的代码.
Verilog has (very) poor checking of bit and part selects and array indexes. See the code below.
module top;
initial
test;
task test;
reg[3:0] a[0:1];
reg[0:3] b[0:1];
reg[2:5] c[0:1];
begin
a[0] = 4'b1101;
a[1] = 4'b0110;
a[2] = 4'b0001; // error, but not caught by Verilog
$display("a[2] is %d", a[2]); // modelsim produces no warning, prints 'a[2] is x'
$display("a[0][4] is %b", a[0][4]); // modelsim warns, and prints 'a[0][4] is x'
$display( // produces '1.1.0.1'
"a[0][3:0] is %b.%b.%b.%b", a[0][3], a[0][2], a[0][1], a[0][0]);
b[0] = a[0];
$display("b[0] is %d", b[0]); // produces '13'
$display( // produces '1.1.0.1'
"b[0][0:3] is %b.%b.%b.%b", b[0][0], b[0][1], b[0][2], b[0][3]);
c[0] = a[0];
$display("c[0] is %d", c[0]); // produces '13'
$display( // produces '1.1.0.1'
"c[0][2:5] is %b.%b.%b.%b", c[0][2], c[0][3], c[0][4], c[0][5]);
end
endtask
endmodule
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