问题描述
什么是 +: 和 -: Verilog/SystemVerilog 运算符?您何时以及如何使用它们?例如:
What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example:
logic [15:0] down_vect;
logic [0:15] up_vect;
down_vect[lsb_base_expr +: width_expr]
up_vect [msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect [lsb_base_expr -: width_expr]
推荐答案
该特定语法称为 索引部分选择.当您需要从多位寄存器内的可变偏移量中选择固定数量的位时，它非常有用.
That particular syntax is called an indexed part select. It's very useful when you need to select a fixed number of bits from a variable offset within a multi-bit register.
以下是语法示例:
reg [31:0] dword;
reg [7:0] byte0;
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;
assign byte0 = dword[0 +: 8]; // Same as dword[7:0]
assign byte1 = dword[8 +: 8]; // Same as dword[15:8]
assign byte2 = dword[16 +: 8]; // Same as dword[23:16]
assign byte3 = dword[24 +: 8]; // Same as dword[31:24]
这种语法的最大优点是可以为索引使用变量.Verilog 中的正常部分选择需要常量.因此，不允许使用 dword[i+7:i] 之类的东西尝试上述操作.
The biggest advantage with this syntax is that you can use a variable for the index. Normal part selects in Verilog require constants. So attempting the above with something like dword[i+7:i] is not allowed.
因此，如果您想使用变量选择选择特定字节，则可以使用索引部分选择.
So if you want to select a particular byte using a variable select, you can use the indexed part select.
使用变量的示例:
reg [31:0] dword;
reg [7:0] byte;
reg [1:0] i;
// This is illegal due to the variable i, even though the width is always 8 bits
assign byte = dword[(i*8)+7 : i*8]; // ** Not allowed!
// Use the indexed part select
assign byte = dword[i*8 +: 8];
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