我如何在 verilog 数组中找到最大数量

问题描述

所以，我有一个 reg[7:0] corr_Output[0:63];，它在我的模块中填充了值.如何在一个 CLK 周期内找到此数组中的最大数量?我写了一个 8 位比较器:

So, I have a reg[7:0] corr_Output[0:63]; which is filled with values in my module. How I can find maximum number in this array at one CLK cycle?I wrote a 8 bit comparator:

module Comparator2D(
input [7:0] X1,
input [7:0] indexX1,
input [7:0] X2,
input [7:0] indexX2,
output [7:0] Y,
output [7:0] indexY
);

always begin
    if (X1 > X2) begin
        Y = X1;
        indexY = indexX1;
    end
    else begin
        Y = X2;
        indexY = indexX2;
    end
end
endmodule

但是我不知道我应该如何在我的顶层设计中实例化这个模块?我想我应该使用for循环"，或者甚至编写另一个模块，它将以金字塔形式连接我的 Comparator2D 模块，但是我发现我无法将整个数组传递给模块的输入端口，所以我有点卡住了..

But I dont know how I should instantiate this module in my top design? I think I should use "for loop", or even write another module which will concatenate my Comparator2D module in pyramid form, but as I found I cant pass whole array to input port of module, so Im a little stuck..

推荐答案

您可以使用 for/generate 来完成，就像在这个代码示例中一样，我可以一次比较 8 个字节.

You can do it by using for/generate, like in this code sample, in which I can compare 8 bytes at a time.

关键是我不能将内存作为输入(一个寄存器数组)传递，但是我可以传递一个位数组来保存内存中的当前值.

The key point is that I cannot pass a memory as input (an array of registers), but I can pass an array of bits that hold the current values from memory.

// This is just your compare module.
module C2D (
    input wire [7:0] X1,
    input wire [7:0] indexX1,
    input wire [7:0] X2,
    input wire [7:0] indexX2,
    output reg [7:0] Y,
    output reg [7:0] indexY
    );

    always @* begin
        if (X1 > X2) begin
            Y = X1;
            indexY = indexX1;
        end
        else begin
            Y = X2;
            indexY = indexX2;
        end
    end
endmodule

// Compare 8 bytes at a time
module greatest8bytes (
    input wire [63:0] array,   // 8 byte array
    output wire [7:0] indexG,
    output wire [7:0] valueG
    );

    wire [7:0] value_l1[0:3];
    wire [7:0] index_l1[0:3];

    genvar i;
    generate
    for (i=0;i<8;i=i+2) begin :gen_comps_l1
        C2D cl1 (array[i*8+7:i*8],
                 i,
                 array[(i+1)*8+7:(i+1)*8],
                 (i+1),
                 value_l1[i/2],
                 index_l1[i/2]
                );
    end
    endgenerate

    wire [7:0] value_l2[0:1];
    wire [7:0] index_l2[0:1];

    generate
    for (i=0;i<4;i=i+2) begin :gen_comps_l2
        C2D cl2 (value_l1[i],
                 index_l1[i],
                 value_l1[i+1],
                 index_l1[i+1],
                 value_l2[i/2],
                 index_l2[i/2]
                );
    end
    endgenerate

    wire [7:0] value_l3[0:0];
    wire [7:0] index_l3[0:0];

    generate
    for (i=0;i<2;i=i+2) begin :gen_comps_l3
        C2D cl3 (value_l2[i],
                 index_l2[i],
                 value_l2[i+1],
                 index_l2[i+1],
                 value_l3[i/2],
                 index_l3[i/2]
                );
    end
    endgenerate

    assign indexG = index_l3[0];
    assign valueG = value_l3[0];
endmodule

greatest8bytes 模块按照您期望的方式合成:作为比较器的金字塔状排列:

The greatest8bytes module is synthesized the way you expect: as a pyramid-like arrangement of comparators:

要将一组 regs(内存)连接到此模块的输入，请创建所需位数(在此示例中为 64)的连线并连接内存的所有元素，就像在此示例模块中一样:

To connect an array of regs (a memory) to the input of this module, create a wire of the desired number of bits (64 in this example) and concatenate all elements of memory, like in this example module:

module findgreatest (
    input wire clk,
    input wire [2:0] addr,
    input wire [7:0] data,
    input wire we,

    output wire [2:0] indexG,
    output wire [7:0] valueG
    );

    reg [7:0] memory[0:7];  // 8 bytes
    // To load data from the outside so the synthesizer won't throw away memory
    always @(posedge clk) begin
        if (we)
            memory[addr] <= data;
    end

    wire [63:0] array = {memory[7],memory[6],memory[5],memory[4],
                         memory[3],memory[2],memory[1],memory[0]};
    greatest8bytes compar (array, indexG, valueG);
endmodule

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