问题描述
我见过很多系统 verilog 程序示例，它们将数据包表示为打包结构.这些数据是否像数据包一样串行传输?系统verilog结构如何在硬件上实现?
I have seen lots of system verilog program examples representing packets of data as a packed structure.Does this data travel serially like a packet? How does a system verilog structure be realized in hardware?
推荐答案
SystemVerilog 中的打包结构只是为您提供了一种通过名称而不是位位置访问信号字段的替代方法.例如
A packed structure in SystemVerilog simply gives you an alternative way to access fields of a signal by name instead of by bit position. For example
typedef struct packed {
logic [2:0] field1; // 3-bits
logic [4:0] field2; // 5-bits
} signal_t; // 8-bits
您现在可以声明具有该类型的连线或变量
You can now declare either a wire or variable with that type
wire signal_t sigA;
var signal_t sigB;
(除了在端口声明中，var 关键字在大多数地方都是隐式的)
(the var keyword is implicit is most places except in a port declaration)
您现在可以以 sigA[7:5] 或 sigA.field1 的形式访问 field1.
You can now access field1 as either sigA[7:5] or sigA.field1.
解包结构，正如 nguthrie 所指出的，提供了变量的分层分组，但它们也提供了比 Verilog 更强的类型.请参阅我的 应用说明 对此.
Unpacked structures, as nguthrie points out, provide a hierarchical grouping of variables, but they also provide a stronger types than Verilog. See my application note on this.
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