问题描述
我正在尝试模拟我的VHDL文件,但是遇到以下错误:
I am trying to simulate my VHDL file, but am running into the following error:
# ** Error: (vcom-11) Could not find work.lab1.
#
# ** Error: (vcom-1195) Cannot find expanded name "work.lab1".
#
# ** Error: Unknown expanded name.
# ** Error: VHDL Compiler exiting
# ** Error: c:/altera/12.1/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./DE2_TOP_run_msim_rtl_vhdl.do line 8
# c:/altera/12.1/modelsim_ase/win32aloem/vcom failed.
# while executing
# "vcom -93 -work work"
在尝试模拟之前,我已经通过Quartus II和ModelSim编译器成功地编译了代码.我的代码中确实有一个lab1实体和体系结构(我什至可以在Quartus Project Navigator的Design Units选项卡中看到它),所以我并不真正理解此错误.有人知道是什么原因造成的吗?
I compiled the code successfully through both Quartus II and the ModelSim compiler before attempting to simulate. I do have a lab1 entity and architecture in my code (I can even see it in the Design Units tab of the Quartus Project Navigator), so I don't really understand this error. Anyone know what's causing this?
推荐答案
当模拟器编译顶层(DE2_TOP)时,它想知道所用组件的外观.因此,在编译上层组件之前,您应该先编译下层组件.
When the simulator is compiling the toplevel (DE2_TOP) it want to know how the used components are like. So, you should have compiled the lowerlevel components before compiling the upperlevel components.
我经常要解决的问题是按正确的顺序编译所有组件,然后使用Modelsim的'vmake'('vmake -work work> work.vmake')命令从库中生成一个makefile (工作).获得makefile后,可以使用(make -f work.vmake)执行它.并且所有文件都将按顺序编译.
What I do most of the times to fix this is compiling all components in correct order and then use the 'vmake' ('vmake -work work > work.vmake') command of Modelsim to generate a makefile out of the library (work). Once you have the makefile you can execute it with (make -f work.vmake). And all files will be compiled in order.
注意:Verilog在这些方面要轻松得多...
Note: Verilog is much more relaxed in those things...
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