问题描述
我曾经使用rdtsc对Linux系统调用进行基准测试，以获取系统调用前后的计数器差异.我将结果解释为墙上时钟计时器，因为TSC以恒定速率递增，并且在进入暂停状态时不会停止.
I used to benchmark Linux System Calls with rdtsc to get the counter difference before and after the system call. I interpreted the result as wall clock timer since TSC increments at constant rate and does not stop when entering halt state.
不变TSC概念描述为
将状态从C0(正在运行)更改为C1(已暂停)时，常量非不变 tsc可以更改频率吗?
Can a constant non-invariant tsc change frequency when changing state from C0 (operating) to C1 (halted)?
我目前的观点是，它不能仅在Performance(P)状态之间更改频率.因此，在使用非不变的tsc时，将rdtsc应用于获取系统调用的挂钟计时器并不可靠.
My current view is that it cannot change frequency only across Performance(P) states. So applying rdtsc to get wall clock timer for system calls is not reliable when using non-invariant tsc.
在我的/proc/cpuinfo中没有找到不变的tsc标志，只有constant_tsc表示这不是必需的不变.
I did not find invariant tsc flag in my /proc/cpuinfo, only constant_tsc meaning that it is not necessary invariant.
混乱的根源是《英特尔系统编程》手册中的一句话:
The source of confusion is the sentence from Intel System Programming manual:
所以某些筹码(包括我的筹码)的tsc不变，但不变.
So some chips (including mine) have constant, but not invariant tsc.
推荐答案
从Nehalem和Saltwell开始，所有Intel处理器都支持不变的TSC，这意味着TSC在P-，C-和T上以恒定速率递增.状态(但不一定跨S状态).
Starting with Nehalem and Saltwell, all Intel processors support invariant TSC, which means that the TSC is incremented at a constant rate across P-, C-, and T-states (but not necessarily across S-states).
从奔腾4家族0F模型03开始，所有英特尔处理器都支持恒定的TSC，这意味着TSC在P状态和T状态之间以恒定速率递增. TSC在HLT状态下继续递增(称为自动停止或C1/自动停止).在任何其他睡眠状态下，TSC都不会增加.这类处理器包括Bonnell.
Starting with Pentium 4 Family 0F Model 03, all Intel processors support constant TSC, which means that the TSC is incremented at a constant rate across P- and T-states. The TSC continues to increment in the HLT state (called Auto Halt or C1/Auto Halt). TSC doesn't increment in any other sleep state. This category of processors includes Bonnell.
较旧的处理器不支持恒定的TSC. TSC在HLT状态下继续递增，但在较深的睡眠状态下则不递增.在这些处理器中的某些处理器上，TSC出错.
Older processors don't support constant TSC. The TSC continues to increment in the HLT state, but not in deeper sleep states. On some of these processors, TSC is buggy.
从S状态唤醒时，TSC值可能会重新初始化(为一些与BIOS相关的值).
The TSC value may be reinitialized (to some BIOS-dependent value) when waking up from an S-state.
这里是摘要. "Y"表示表示TSC在指定的状态类型中继续以相同的速率递增. "N"表示意味着TSC要么继续以不同的速率递增，要么停止递增.在一些处理器上，TSC在S3状态下递增并降低(这称为永远在线TSC). "N/A"表示不适用".表示不支持TSC.
Here is a summary. "Y" means that TSC continues to increment at the same rate across the specified type of states. "N" means that TSC either continues to increment at a different rate or stops incrementing. On a few processors, TSC is incremented in the S3 state and lower (this is called always-on TSC). "N/A" means that TSC is not supported.
| T | P |C = HLT|C Other|S <= S3|S Other|
---------------------------------------------------
Nehalem+ | Y | Y | Y | Y | N | N |
Silvermont Merrifield+Moorefield, | Y | Y | Y | Y | Y | N |
Saltwell Penwell+Cloverview
Other Saltwell+ | Y | Y | Y | Y | N | N |
KNL+ | Y | Y | Y | Y | N | N |
P4 90nm+ | Y | Y | Y | N | N | N |
Enhanced Pentium M+ | Y | Y | Y | N | N | N |
Bonnell | Y | Y | Y | N | N | N |
Quark X1000 | Y | N | Y | N | N | N |
KNC | Y | N | Y | N | N | N |
P5+ | Y | N | Y | N | N | N |
Before P5 | N/A | N/A | N/A | N/A | N/A | N/A |
Other Quark | N/A | N/A | N/A | N/A | N/A | N/A |
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