如何在ARM体系结构中读取协处理器寄存器

问题描述

我正在尝试在以下片上系统中读取CP15协处理器

I'm trying to read CP15 coprocessor in the following System-on-chip

Cortex A7-ARMv7-A

Cortex A7 - ARMv7-A

在我的代码段下面

void main (void)
{
    unsigned int reg_value = 0;
    asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(reg_value) );
    printf("reg_value: %d", reg_value);
}

我不知道这是否是读取协处理器寄存器的正确方法，但其编译已完成且没有错误.在执行过程中会出现问题(代码在根目录下执行):

I don't know if this is the correct way to read the coprocessor register but its compilation is completed without errors.The problem is arisen during its execution (the code is executed in root):

Illegal instruction

如果我使用gdb，则会得到以下结果:

If I use gdb I obtain the following result:

   0x000086a0 <+16>:    str r3, [r11, #-40] ; 0x28
=> 0x000086a4 <+20>:    mrc 15, 0, r3, cr0, cr0, {0}
   0x000086a8 <+24>:    str r3, [r11, #-40] ; 0x28

为什么我无法读取协处理器寄存器?我的代码有什么问题?

Why I'm not able to read coprocessor registers? What's wrong with my code?

推荐答案

似乎您正在尝试使用以下指令访问MIDR:主ID寄存器(来自ARMARMv7 B4.1.105)

It seems that you are trying to access MIDR: Main ID Register (from the ARMARMv7 B4.1.105) using the instruction

MRC p15, 0, <Rt>, c0, c0, 0    ; Read MIDR into Rt

但是，就像在Linux中执行应用程序一样，您处于用户模式(PL0)并且ARMARMv7在MIDR的使用限制中指定了

However, as you are in Linux and executing an application, you are in usermode (PL0)and ARMARMv7 specifies in the usage constraints of MIDR that

因此仅可在PL1，PL2，PL3访问.要访问它，您需要创建一个在PL1运行的驱动程序，它将读取MIDR.然后，在您的应用程序中，例如，使用IOCTL打开此驱动程序以获取数据.

So only accessible at PL1, PL2, PL3. To access it you need to create a driver running at PL1 which will do the read of MIDR. Then, in your application, open this driver to get the data using IOCTL for example.

您还可以尝试使用PL0中的SVC调用来访问内核模式(PL1)，但这将意味着修改内核SVC处理程序.

You can also try to access the kernel mode (PL1) using a SVC call from PL0, but this would imply modifying your kernel SVC handler.

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