无法推断...在...处的寄存器，因为它不在时钟沿以外保持其值

问题描述

这一定是VHDL初学者中最常见的问题，但是我看不出我在做什么错！这似乎符合我在适当的状态机设计上看到的所有惯用法.我正在用Altera Quartus 9.2进行编译，以了解它的价值.实际错误是:

This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's worth. The actual error is:

无法在[文件] [行]处推断"spiclk_out"的注册，因为它不在时钟沿之外保存其值"

"Can't infer register for "spiclk_out" at [file] [line] because it does not hold its value outside the clock edge"

ENTITY spi_state_machine IS
    PORT(
            spiclk_internal : IN STD_LOGIC;
            reset : IN STD_LOGIC;
            spiclk_out : BUFFER STD_LOGIC
    );
END spi_state_machine;

PROCESS(spiclk_internal, reset)
BEGIN
    IF reset = '1' THEN
        spiclk_out <= '0';
    END IF;

    IF spiclk_internal = '1' AND spiclk_internal'EVENT THEN --error here
        spiclk_out <= NOT spiclk_out;
    END IF;
END PROCESS;

感谢您的时间.

推荐答案

如所写，即使reset处于活动状态，该过程也会导致spiclk_out在spiclk_internal边沿上切换，这与触发器无关.异步重置应该起作用.

As written, the process would cause spiclk_out to toggle on spiclk_internal edges even when reset is active, which is not how flip-flops with asynchronous resets should behave.

您可能想要的是

SPICLK: process(spiclk_internal, reset)
    if reset = '1' then
        spiclk_out <= '0';
    elsif spiclk_internal'event and spiclk_internal='1' then
        spiclk_out <= not spiclk_out;
    end if;
end process SPICLK;

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