问题描述
为解决Verilog中由不同时钟域引起的亚稳态，使用了双寄存器方法。
For solving metastability caused by different clock domains in Verilog, double-register method is used.
但是据我所知，亚稳态的最终输出不确定。输出独立于输入。
But as far as I know, the final output of metastability is undetermined. Output is independent of input.
所以，我的问题是如何使用双寄存器方法保证输出的正确性？
So, my question is how to guarantee the correctness of output using double-register method?
谢谢。
推荐答案
您不能完全确定自己是否避免了亚稳性。
正如您提到的，亚稳态触发器的输出是不可预测的，因此即使具有双寄存器方法，当您具有亚稳态时，也可能传播错误的值。
You cannot be completely sure that you avoided metastability.As you mentioned, the output of a metastable flip-flop is unpredictable so you can potentially propagate a wrong value when you have metastability even with the 'two-register' approach.
此方法从不打算解决亚稳性，而是尝试降低亚稳值进入电路的可能性。所谓的 MTBF（平均无故障时间）。为了减少MTBF，您甚至可以链接两个以上的寄存器。
This method however never intended to solve metastability but tries to reduce the probability that a metastable value enters your circuit. What is called here MTBF (Mean Time Between Failure). To reduce the MTBF you can even chain more that 2 registers.
即使这不能解决值的不确定性，使用这些双寄存器也很有趣。因为当一个值是亚稳态时，它将一直振荡直到稳定到0或1。
Even if this does not solve the unpredictive-ness of a value, it is interesting to use these double registers because when a value is metastable, it will oscillate until it stabilize to 0 or 1.
这种振荡将使您的电路切换，然后大量消耗能量，因为每个过渡过程都消耗能量。因此，使用双寄存器进行时钟域穿越非常重要。
This oscillation will make your circuit toggle and then use a lot of energy for nothing as each transition consumes energy. That for this reason that it is important to use double registers for clock-domain crossing.
为了确保数据有效，您可以使用请求确认机制在两个时钟域之间。
To ensure that you data is valid though, you can use a request-acknowledge mechanism between the two clock-domains.
快速示例：
- 设置数据到总线（双寄存器的输入）
- 等待1个（或更多）时钟周期，以确保在另一侧建立良好的数据
- 发送请求信号（双寄存器输入）
- 最坏的情况：请求信号是亚稳态的，并且一旦稳定就保持为0。下一个时钟周期将为1，因为它已经设置为1至少一个时钟周期。最好的情况：下一个周期，目的地将接受数据
- 数据稳定，请求稳定，并且在1->可以使用数据。向源发送确认。
- 确认到达（在亚稳态情况下在双寄存器上）。如果为亚稳态，则可能需要更多的时钟周期。
- 请求下降。
- 可以通过总线发送其他数据
- Set the data to the bus (input of a double registers)
- Wait 1(or more) clock cycle to be sure the data is well established on the other side
- Send a request signal (input of a double register)
- Worst case : The request signal is metastable and stays at 0 once stabilized. Next clock cycle it will be at 1 as it would be already set to 1 for at least 1 clock cycle. Best case : next cycle the destination will accept the data
- The data is stable, the request is stable and at 1 -> the data can be consumed. Send an acknowledgement to the source.
- The acknowledgement arrives (on a double register in case of metastability). If metastable it can take a clock cycle more to arrive.
- Request falls.
- Another data can be sent via the bus
该协议称为4相协议协议。您可以在网上找到很多有关它的文档，因为它是异步设计的经典协议。
This protocol is called a 4-phase protocol. You can find a lot of documentation about it on the web as it is a classic protocol for asynchronous designs.
它非常容易理解和实现。请记住，尽管这会在区域中产生非常重要的开销。
It is quite simple to understand and to implement. Keep in mind though that it will generate an overhead in area that can be quite important.
希望它会有所帮助。
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