if rising_edge(CLK_100Mhz) then
if w_ram = '1' then
for X in 0 to 6 loop
for Y in 0 to 6 loop
DataO(X)(Y)(0) <= Memory(X)(Y)(Address);
DataO(X)(Y)(1) <= Memory(X)(Y)(Address+1);
DataO(X)(Y)(2) <= Memory(X)(Y)(Address+2);
DataO(X)(Y)(3) <= Memory(X)(Y)(Address+3);
Memory(X)(Y)(Address) <= DataI(X)(Y)(0);
end loop;
end loop;
w_ram <= '0';
end if;
end if;
我需要为我的数据密集型项目使用Block ram。对于给定的X，Y，这将是一个1输入，4输出的块，还是对于给定的X，Y，这将创建4个块？这也行吗？我正在使用Xilinx Zynq-7000 FPGA。
谢谢。
最佳答案
我猜您想让Xilinx综合工具推断出多个不对称的Block RAM。 Xilinx具有可推断一个RAM的示例代码，可以在以下位置找到
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst_v6s6.pdf
写端口为8位宽和256深度，读端口为32位宽和64深度。这是上面链接的代码：
-- Asymmetric port RAM
-- Port A is 256x8-bit write-only
-- Port B is 64x32-bit read-only
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/asymmetric_ram_1a.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity asymmetric_ram_1a is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
weA : in std_logic;
enA : in std_logic;
enB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diA : in std_logic_vector(WIDTHA-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end asymmetric_ram_1a;
architecture behavioral of asymmetric_ram_1a is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE : integer := max(SIZEA,SIZEB);
constant RATIO : integer := maxWIDTH / minWIDTH;
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
signal ram : ramType := (others => (others => '0'));
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) <= diA;
end if;
end if;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
readB(minWIDTH-1 downto 0)
<= ram(conv_integer(addrB&conv_std_logic_vector(0,2)));
readB(2*minWIDTH-1 downto minWIDTH)
<= ram(conv_integer(addrB&conv_std_logic_vector(1,2)));
readB(3*minWIDTH-1 downto 2*minWIDTH)
<= ram(conv_integer(addrB&conv_std_logic_vector(2,2)));
readB(4*minWIDTH-1 downto 3*minWIDTH)
<= ram(conv_integer(addrB&conv_std_logic_vector(3,2)));
end if;
regB <= readB;
end if;
end process;
doB <= regB;
end behavioral;
这是综合报告的摘录，确认XST推断出非对称内存。
Synthesizing (advanced) Unit <asymmetric_ram_1a>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <readB> <regB>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 256-word x 8-bit | |
| mode | write-first | |
| clkA | connected to signal <clkA> | rise |
| weA | connected to signal <weA_0> | high |
| addrA | connected to signal <addrA> | |
| diA | connected to signal <diA> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 64-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <clkB> | rise |
| enB | connected to signal <enB> | high |
| addrB | connected to signal <addrB> | |
| doB | connected to signal <doB> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <asymmetric_ram_1a> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
256x8:64x32-bit dual-port block RAM : 1
请注意，尽管综合报告说了什么，但端口B是只读的。
关于vhdl - 具有多个输出的VHDL合成滑块，我们在Stack Overflow上找到一个类似的问题：https://stackoverflow.com/questions/29239911/