verilog - 为什么If语句在verilog中导致闩锁？

我正在尝试在Verilog中编写 Controller /数据路径实现的代码，而我对导致意外闩锁的原因感到困惑。本质上，我在状态时钟上更新了状态机。该状态机根据机器所处的状态将5个控制信号(loadSquare，loadDelta，addDelta等)发送到数据路径。下面显示了数据路径和 Controller 的代码。

数据路径

//Control lines
reg addSquare, addDelta, decDelta;
reg loadSquare, loadDelta;

//Input lines
reg [8:0] square, delta;

//Output register
reg [7:0] outReg;

always @(posedge clk) begin
  if (loadSquare)
     square = 9'h1;  //used on initialization

  if (loadDelta)
     delta = 9'h3;   //used on initialization

  if (addSquare)
     square = square + delta;

  if (addDelta)
     delta = delta + 2'h2;

  if (decDelta)
     outReg = (delta>>1) - 1;  //used for output
  else
     outReg = Input;
end

Controller

//Output of module
assign Output = outReg;

//Finite State Machine
always @(currentState) begin
    case(currentState)
        2'h0:   begin       //initialize values, wait for start
        {loadSquare, loadDelta} = 2'b11;
        {addSquare, addDelta, decDelta} = 3'h0;
     end
        2'h1: begin
        {loadSquare, loadDelta} = 2'b00;
        {addSquare, addDelta, decDelta} = 3'b110;  //add square and delta
     end
        2'h2: begin
        {loadSquare, loadDelta} = 2'b00;
        {addSquare, addDelta, decDelta} = 3'b001;  //decrement delta, wait for reset
     end
        default: ; // unused
    endcase

//Next state logic implemented on negedge clk (not shown)

此代码在Xilinx中生成以下警告:

WARNING:Xst:737 - Found 1-bit latch for signal <addDelta>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <decDelta>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <loadDelta>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:1294 - Latch <loadDelta> is equivalent to a wire in block <ModuleName>.
WARNING:Xst:1294 - Latch <decDelta> is equivalent to a wire in block <ModuleName>.
WARNING:Xst:1294 - Latch <addDelta> is equivalent to a wire in block <ModuleName>.

我了解不完整的if语句会导致闩锁。为了解决这个问题，我尝试了2种不同的实现，但是它们没有删除警告。对于“decDelta”案例，我尤其感到困惑，因为我不明白我在此条件声明中没有解释什么。

尝试＃1

always @(posedge clk) begin
  if (loadSquare)
     square = 9'h1;
  else
     square = square;

  if (loadDelta)
     delta = 9'h3;
  else
     delta = delta;

  //... and so on

尝试＃2

always @(posedge clk) begin
  square = square;
  delta = delta;

  if (loadSquare)
     square = 9'h1;

  if (loadDelta)
     delta = 9'h3;

  //... and so on

运行模拟时，代码可以按预期工作，但是我想了解更多有关导致这些警告的原因。

最佳答案

锁存器是基本的存储元件，它是打开或关闭的，即它是电平敏感的。触发器基本上是两个锁存器，一个锁存器对使能信号的反相进行操作，这使其对边沿敏感。

使用always @(posedge clk)时，您隐含了一个在clk的上升沿加载数据值的触发器。在此过程中不会隐含闩锁(always @(posedge clk))。

如Sharvil111所述，当您在组合部分(即always @*进程)中留下 undefined 的状态时，就会隐含闩锁。如果某些东西在条件部分中 undefined ，那么它将保留其值。值保留是状态，并且由于组合部分对边缘不敏感，因此您已强制该工具插入闩锁。

为了避免这种情况，请完全定义条件输出:

always @(currentState) begin
case(currentState)
    2'h0:   begin       //initialize values, wait for start
    {loadSquare, loadDelta} = 2'b11;
    {addSquare, addDelta, decDelta} = 3'h0;
 end
    2'h1: begin
    {loadSquare, loadDelta} = 2'b00;
    {addSquare, addDelta, decDelta} = 3'b110;  //add square and delta
 end
    2'h2: begin
    {loadSquare, loadDelta} = 2'b00;
    {addSquare, addDelta, decDelta} = 3'b001;  //decrement delta, wait for reset
 end
    default: begin
    {loadSquare, loadDelta} = 2'b00;
    {addSquare, addDelta, decDelta} = 3'b000;
    end
endcase