Verilog手绘FVH信号
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2018/09/17 13:20:06
// Design Name:
// Module Name: ntsc_fvh
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module ntsc_fvh( input wire clk, //27MHz
input wire rst,
input wire enable, output wire hsout,
output wire vsout,
output wire oeout ); parameter THSOUT = ; //2.4us
parameter H_TOTAL = ; //64us
parameter V_TOTAL = ; wire hsout_falling; //------------------------------------------------- reg [:]hsout_cnt = ;
always @(posedge clk or posedge rst)
begin
if(rst)
hsout_cnt <= ; else if(enable)
begin
if(hsout_cnt == H_TOTAL)
hsout_cnt <= ;
else
hsout_cnt <= hsout_cnt + 'b1;
end else
hsout_cnt <= ; end //------------------------------------------------- reg hsout_reg = 'b1 ;
always @(posedge clk or posedge rst)
begin
if(rst)
hsout_reg <= 'b1; else if(enable)
begin
if(hsout_cnt <= THSOUT - || hsout_cnt == H_TOTAL)
hsout_reg <= 'b0;
else if(hsout_cnt >= THSOUT && hsout_cnt <= H_TOTAL - )
hsout_reg <= 'b1;
end else
hsout_reg <= 'b1;
end //------------------------------------------------- reg hsout_reg_delay = 'b1;
always @(posedge clk or posedge rst)
begin
if(rst)
hsout_reg_delay <= 'b1; else if(enable)
hsout_reg_delay <= hsout_reg; else
hsout_reg_delay <= 'b1; end //------------------------------------------------- reg [:] hsout_falling_cnt = ;
always @(posedge clk or posedge rst)
begin
if(rst)
hsout_falling_cnt <= ; else if(enable)
begin if(hsout_falling_cnt == V_TOTAL)
begin
hsout_falling_cnt <= V_TOTAL;
if(hsout_falling)
hsout_falling_cnt <= ;
end else if(hsout_falling)
hsout_falling_cnt <= hsout_falling_cnt + 'b1;
end else
hsout_falling_cnt <= 'b0; end //------------------------------------------------- reg vsout_reg = 'b1;
reg oeout_reg = 'b0;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
vsout_reg <= 'b1;
oeout_reg <= 'b0;
end else if(enable)
begin if(hsout_falling_cnt < || (hsout_falling_cnt == && hsout_cnt < && hsout_cnt >))
begin
vsout_reg <= 'b1;
oeout_reg <= 'b0;
end else if(hsout_falling_cnt == && hsout_cnt == )
begin
vsout_reg <= 'b0;
oeout_reg <= 'b1;
end else if(hsout_falling_cnt == && hsout_cnt == )
vsout_reg <= 'b1; else if(hsout_falling_cnt == && hsout_cnt == )
begin
vsout_reg <= 'b0;
oeout_reg <= 'b0;
end else if(hsout_falling_cnt == && hsout_cnt == )
vsout_reg <= 'b1; else
begin
vsout_reg <= vsout_reg;
oeout_reg <= oeout_reg;
end
end
end //------------------------------------------------- assign hsout_falling = hsout_reg_delay && (!hsout_reg);
assign hsout = hsout_reg;
assign vsout = vsout_reg;
assign oeout = oeout_reg; endmodule /* add_force {/ntsc_fvh/clk} -radix hex {1 0ns} {0 25000ps} -repeat_every 50000ps
add_force {/ntsc_fvh/rst} -radix hex {1 0ns} {0 100ns}
add_force {/ntsc_fvh/enable} -radix hex {1 0ns} */
仿真结果：