uvm_reg_item——寄存器模型（五）

　　uvm_reg_item 扩展自uvm_sequence_item，也就说寄存器模型定义了transaction item. adapter 的作用是把这uvm_reg_item转换成uvm_sequence_item，再经由uvm_sequencer发送个uvm_driver，最终在总线上传输。

//------------------------------------------------------------------------------

// Title: Generic Register Operation Descriptors

//

// This section defines the abstract register transaction item. It also defines

// a descriptor for a physical bus operation that is used by <uvm_reg_adapter>

// subtypes to convert from a protocol-specific address/data/rw operation to

// a bus-independent, canonical r/w operation.

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

// CLASS: uvm_reg_item

//

// Defines an abstract register transaction item. No bus-specific information

// is present, although a handle to a <uvm_reg_map> is provided in case a user

// wishes to implement a custom address translation algorithm.

//------------------------------------------------------------------------------

class uvm_reg_item extends uvm_sequence_item;

  `uvm_object_utils(uvm_reg_item)

  // Variable: element_kind

  //

  // Kind of element being accessed: REG, MEM, or FIELD. See <uvm_elem_kind_e>.

  //

  uvm_elem_kind_e element_kind;

  uvm_object element;

  rand uvm_access_e kind;

  // Variable: value

  //

  // The value to write to, or after completion, the value read from the DUT.

  // Burst operations use the <values> property.

  //

  rand uvm_reg_data_t value[];

  // TODO: parameterize

  constraint max_values { value.size() >  && value.size() < ; }

  rand uvm_reg_addr_t offset;

  uvm_status_e status;

  uvm_reg_map local_map;

  uvm_reg_map map;

  uvm_path_e path;

  rand uvm_sequence_base parent;

  int prior = -;

  rand uvm_object extension;

  string bd_kind;

  string fname;

  int lineno;

  function new(string name="");

    super.new(name);

    value = new[];

  endfunction

  // Function: convert2string

  //

  // Returns a string showing the contents of this transaction.

  //

  virtual function string convert2string();

    string s,value_s;

    s = {"kind=",kind.name(),

         " ele_kind=",element_kind.name(),

         " ele_name=",element==null?"null":element.get_full_name() };

    if (value.size() >  && uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin

      value_s = "'{";

      foreach (value[i])

         value_s = {value_s,$sformatf("%0h,",value[i])};

      value_s[value_s.len()-]="}";

    end

    else

      value_s = $sformatf("%0h",value[]);

    s = {s, " value=",value_s};

    if (element_kind == UVM_MEM)

      s = {s, $sformatf(" offset=%0h",offset)};

    s = {s," map=",(map==null?"null":map.get_full_name())," path=",path.name()};

    s = {s," status=",status.name()};

    return s;

  endfunction

  virtual function void do_copy(uvm_object rhs);

  endfunction

endclass

//------------------------------------------------------------------------------

//

// CLASS: uvm_reg_bus_op

//

// Struct that defines a generic bus transaction for register and memory accesses, having

// ~kind~ (read or write), ~address~, ~data~, and ~byte enable~ information.

// If the bus is narrower than the register or memory location being accessed,

// there will be multiple of these bus operations for every abstract

// <uvm_reg_item> transaction. In this case, ~data~ represents the portion

// of <uvm_reg_item::value> being transferred during this bus cycle.

// If the bus is wide enough to perform the register or memory operation in

// a single cycle, ~data~ will be the same as <uvm_reg_item::value>.

//------------------------------------------------------------------------------

typedef struct {

  // Variable: kind

  //

  // Kind of access: READ or WRITE.

  //

  uvm_access_e kind;

  // Variable: addr

  //

  // The bus address.

  //

  uvm_reg_addr_t addr;

  // Variable: data

  //

  // The data to write. If the bus width is smaller than the register or

  // memory width, ~data~ represents only the portion of ~value~ that is

  // being transferred this bus cycle.

  //

  uvm_reg_data_t data;

  // Variable: n_bits

  //

  // The number of bits of <uvm_reg_item::value> being transferred by

  // this transaction.

  int n_bits;

  /*

  constraint valid_n_bits {

     n_bits > 0;

     n_bits <= `UVM_REG_DATA_WIDTH;

  }

  */

  // Variable: byte_en

  //

  // Enables for the byte lanes on the bus. Meaningful only when the

  // bus supports byte enables and the operation originates from a field

  // write/read.

  //

  uvm_reg_byte_en_t byte_en;

  // Variable: status

  //

  // The result of the transaction: UVM_IS_OK, UVM_HAS_X, UVM_NOT_OK.

  // See <uvm_status_e>.

  //

  uvm_status_e status;

} uvm_reg_bus_op;