首先这是产生aixs数据流的代码
`timescale 1ps/1ps `default_nettype none module
axis_switch_0_example_master #(
parameter integer C_MASTER_ID =
)
(
/**************** Stream Signals ****************/
output reg m_axis_tvalid = ,
input wire m_axis_tready,
output wire [-:] m_axis_tdata,
output wire [/-:] m_axis_tkeep,
output reg m_axis_tlast = ,
output wire [-:] m_axis_tuser,
/**************** System Signals ****************/
input wire aclk,
input wire aresetn,
/**************** Done Signal ****************/
output reg done =
); /**************** Local Parameters ****************/
localparam integer P_M_TDATA_BYTES = / ;
localparam integer P_M_TUSER_BYTES = ;
localparam [-:] P_M_PACKET_SIZE = ( - );
localparam [-:] P_M_PACKET_NUM = ;
localparam [-:] P_M_SINGLES_NUM = ;
localparam [-:] P_M_DONE_NUM = ;
localparam integer P_M_NUM_MI_SLOTS = ;
localparam integer P_M_NUM_SI_SLOTS = ;
localparam [P_M_NUM_MI_SLOTS*P_M_NUM_SI_SLOTS-:] P_M_CONNECTIVITY_ARRAY = 'b11;
localparam [*P_M_NUM_SI_SLOTS-:] P_M_NUM_CONNECTED_MI_ARRAY = {'d2};
localparam integer P_M_NUM_CONNECTED_MI = P_M_NUM_CONNECTED_MI_ARRAY[C_MASTER_ID*+:]; /**************** Internal Wires/Regs ****************/
genvar i;
generate
for(i=; i<P_M_TDATA_BYTES; i=i+) begin: tdata_g
reg [-:] tdata_i = 'h00;
end
endgenerate
generate
for(i=; (i<P_M_TUSER_BYTES-); i=i+) begin: tuser_g
reg [-:] tuser_i = 'h00;
end
endgenerate
reg [( - (*(P_M_TUSER_BYTES-)) - ):] tuser_i;
reg [-:] pcnt_i = 'h0000;
reg [-:] tcnt_i = 'h0000;
wire done_i;
wire transfer_i;
wire areset = ~aresetn;
reg [-:] areset_i = 'b00; /**************** Assign Signals ****************/
assign m_axis_tkeep = {P_M_TDATA_BYTES{'b1}};
generate
for(i=; i<P_M_TDATA_BYTES; i=i+) begin: tdata_assign_g
assign m_axis_tdata[*i +: ] = tdata_g[i].tdata_i[:];
end
endgenerate
generate
for(i=; i<P_M_TUSER_BYTES; i=i+) begin: tuser_assign_g
if(i == (P_M_TUSER_BYTES - )) begin: tuser_assign_upper_g
assign m_axis_tuser[- : *i] = tuser_i;
end
else begin: tuser_assign_lower_g
assign m_axis_tuser[*i +: ] = tuser_g[i].tuser_i[:];
end
end
endgenerate
assign transfer_i = m_axis_tready && m_axis_tvalid; generate
if(!P_M_NUM_CONNECTED_MI) begin: unconnected_master_g
assign done_i = 'b1;
end
else begin: connected_master_g
assign done_i = (transfer_i && (pcnt_i == P_M_DONE_NUM - 'b1) && (tcnt_i == P_M_PACKET_SIZE));
end
endgenerate // Register Reset
always @(posedge aclk) begin
areset_i <= {areset_i[], areset};
end //**********************************************
// TDATA
//**********************************************
generate
for(i=; i<P_M_TDATA_BYTES; i=i+) begin: tdata_incr_g
always @(posedge aclk) begin
if(areset) begin
tdata_g[i].tdata_i <= 'h00;
end
else
begin
tdata_g[i].tdata_i <= (transfer_i) ? (tdata_g[i].tdata_i + 'b1) : (tdata_g[i].tdata_i);
end
end
end
endgenerate //**********************************************
// TUSER
//**********************************************
generate
for(i=; (i<P_M_TUSER_BYTES-); i=i+) begin: tuser_incr_g
always @(posedge aclk) begin
if(areset) begin
tuser_g[i].tuser_i <= {( - (*i)){'b1}};
end
else
begin
tuser_g[i].tuser_i <= (transfer_i) ? (tuser_g[i].tuser_i - 'b1) : (tuser_g[i].tuser_i);
end
end
end
endgenerate always @(posedge aclk) begin
if(areset) begin
tuser_i <= {( - (*(P_M_TUSER_BYTES-))){'b1}};
end
else
begin
tuser_i <= (transfer_i) ? (tuser_i - 'b1) : tuser_i;
end
end //**********************************************
// TVALID
//**********************************************
always @(posedge aclk) begin
if(areset) begin
m_axis_tvalid <= 'b0;
end
else
begin
// TVALID
if(done_i) begin
m_axis_tvalid <= 'b0;
end
else if(areset_i == 'b10) begin
m_axis_tvalid <= 'b1;
end
else begin
m_axis_tvalid <= m_axis_tvalid;
end
end
end //**********************************************
// TLAST
//**********************************************
always @(posedge aclk) begin
if(areset) begin
m_axis_tlast <= 'b0;
end
else
begin
// TLAST
if(areset_i == 'b10) begin
m_axis_tlast <= 'b1;
end
else if((pcnt_i >= (P_M_SINGLES_NUM - 'b1)) && transfer_i && m_axis_tlast) begin
m_axis_tlast <= 'b0;
end
else if(tcnt_i == (P_M_PACKET_SIZE - 'b1) && transfer_i) begin
m_axis_tlast <= 'b1;
end
else begin
m_axis_tlast <= m_axis_tlast;
end
end
end //**********************************************
// PCNT, TCNT, DONE
//**********************************************
always @(posedge aclk) begin
if(areset) begin
pcnt_i <= 'h0000;
tcnt_i <= 'h0000;
done <= 'b0;
end
else
begin
// DONE
done <= (done_i) ? 'b1 : done; // Increment counters
tcnt_i <= (transfer_i) ? (m_axis_tlast ? 'h0000 : (tcnt_i + 1'b1)) : tcnt_i;
pcnt_i <= (transfer_i && m_axis_tlast) ? (pcnt_i + 'b1) : pcnt_i;
end
end endmodule `default_nettype wire
这里是仿真的代码
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/08/02 15:17:37
// Design Name:
// Module Name: test_axis_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module test_axis_tb( ); reg aclk=;
reg aresetn=;
wire s_axis_tvalid;
wire [-:]s_axis_tdata;
wire [/-:] s_axis_tkeep;
wire s_axis_tlast;
wire [-:]s_axis_tuser;
reg s_axis_tready=;
wire example_master_done;
// Example master #0
axis_switch_0_example_master #(
.C_MASTER_ID ( )
) inst_axis_switch_0_example_master_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.m_axis_tvalid ( s_axis_tvalid),
.m_axis_tdata ( s_axis_tdata ),
.m_axis_tkeep ( s_axis_tkeep ),
.m_axis_tlast ( s_axis_tlast ),
.m_axis_tuser ( s_axis_tuser),
.m_axis_tready ( s_axis_tready ),
.done ( example_master_done )
);
always # aclk=~aclk;
initial begin
# s_axis_tready=;
# s_axis_tready=;
end
initial begin # aresetn=;
# aresetn=;
end
endmodule