关于FIFO异步复位的问题

关于FIFO异步复位的问题

FIFO异步复位的宽度，需要保证至少3个较慢时钟的时钟周期长度。

怎样对一个脉冲加宽呢？

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 2018/08/08 19:03:20

// Design Name:

// Module Name: signal_wide

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module signal_wide(

    input  wire  clk,

    input  wire  rst,

    input  wire  signal

    );

reg [:] signal_delay = ;

reg       signal_delay_wide = ;

always @ (posedge clk or posedge rst)

begin

    if(rst)

    begin

        signal_delay <= 'b0;

        signal_delay_wide <= 'b0;

    end

    else

    begin

        signal_delay <= {signal_delay[:],signal};

        signal_delay_wide <= | signal_delay;

    end

end

endmodule

/*

add_force {/signal_wide/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps

add_force {/signal_wide/rst} -radix hex {1 0ns} {0 200ns}

add_force {/signal_wide/signal} -radix hex {0 0ns} {1 600ns} {0 700ns}

*/