2. 引导代码执行完 CPU/DRAM/CLOCK/UART初始化后,就可以把跑在RAM空间的UBOOT代码下载对应位置进行引导,则会有对应得到控制台console shell, 用户则可以通过console shell 输入命令后即可操作 串口/tftp/ 和 nandflash 了。
一般从 UBOOT/arch/arm/xxx/start.S 超出对应的部分即可。
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- .text
- .globl _start
- /*
- * the actual start code
- */
- _start:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0, cpsr
- bic r0, r0, #0x1f
- orr r0, r0, #0xd3
- msr cpsr, r0
- /*
- * disable WatchDog
- */
- mov r0, #0x53000000 @ ldr r0, =pWTCON
- mov r1, #0
- str r1, [r0] @ disable WTCON
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =0x4a000008 @ldr r0, =INTMSK
- str r1, [r0]
-
- System_Clock_Init:
- /* Clock asynchronous mode */
- mrc p15, 0, r1, c1, c0, 0
- orr r1, r1, #0xc0000000
- mcr p15, 0, r1, c1, c0, 0
- ldr r0, =0x4c000000
- /* LOCKTIME configure */
- ldr r1, =0xffffff
- str r1, [r0, #0x0] @LOCKTIME
- /* CAMDIVN configure */
- ldr r1, =0x0
- str r1, [r0, #0x18] @CAMDIVN
- /*
- * default FCLK is 120 MHz !
- * FCLK:HCLK:PCLK = 1:4:8
- */
- ldr r1, =0x05
- str r1, [r0, #0x14] @CLKDIVN 1:4:8
-
- /* UPLL setup */ @ USB clock to 48MHz
- ldr r1, =((56 << 12) | (2 << 4) | (2))
- str r1, [r0, #0x08]
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* MPLL setup */ @ Main clock to 405MHz
- ldr r1, =((127 << 12) | (2 << 4) | (1))
- str r1, [r0, #0x04]
-
- cpu_init_crit:
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
- mcr p15, 0, r0, c1, c0, 0
- Memory_Initial:
- adrl r0, mem_cfg_val
- mov r1, #0x48000000
- add r3, r1, #52
-
- 1: ldr r4, [r0], #4
- str r4, [r1], #4
- cmp r1, r3
- bne 1b
- mov r2, #0x8000000
- loop:
- subs r2, r2, #1
- bne loop @ dead loop
- .align 4
- mem_cfg_val:
- .long 0x01001000 @BWSCON
- .long 0x00 @BANKCON0
- .long 0x00 @BANKCON1
- .long 0x00 @BANKCON2
- .long 0x1FC0 @BANKCON3
- .long 0x00 @BANKCON4
- .long 0x00 @BANKCON5
- .long 0x00018005 @BANKCON6
- .long 0x00 @BANKCON7
- .long 0x009c04f5 @ HCLK=100MHz
- .long 0x000000b0
- .long 0x00000030 @Bank Size
- .long 0x00000000 @MRSR
其中主要的部分为 把部分 lowlevel_init.S 中对 MPLL/CLKDIVN 和 DRAM的配置部分提前拿到这里。
即初始化的部分为 保证 CPU/RAM能用, clock能跑起来就OK了。
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- objs := init.o
- all: $(objs)
- arm-elf-ld -Ttext 0x0000000 -o init_elf $^
- arm-elf-objcopy -O binary -S init_elf init.bin
- arm-elf-objdump -D -m arm init_elf > init.dis
-
- %.o:%.c
- arm-elf-gcc -Wall -g -c -o $@ $<
- %.o:%.S
- arm-elf-gcc -Wall -g -c -o $@ $<
- clean:
- rm -f init.bin init_elf init.dis *.o
jlink的使用:
jlink.bat =>
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- "D:\SEGGER\V408l\JLink.exe" jlink_script.txt
- @echo "OK"
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- speed 1200
- h
- loadbin init.bin 0
- setpc 0
- g
- sleep 100
- h
- loadbin u-boot.ram.bin 0x31F80000
- setpc 0x31F80000
- g
- q