board.c: start_armboot()1.lcd frame buffer的保留机理:#ifdef CONFIG_LCD#    ifndef PAGE_SIZE#      define PAGE_SIZE 4096#    endif    /*     * reserve memory for LCD display (always full pages)     */    /* bss_end is defined in the board-specific linker script */    addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);    size = lcd_setmem (addr);    gd->fb_base = addr;#endif /* CONFIG_LCD */1)==> CONFIG_LCD  in include/configs/smdk6410.h  ==> PAGE_SIZE same as above不同的芯片,不同的PAGE_SIZE,不同的LCD有无的配置  2)_bss_endcpu/s3c64xx/start.S:.globl _bss_start_bss_start:    .word __bss_start.globl _bss_end_bss_end:    .word _end    3)boarc/samsung/smdk6410/u-boot.lds:    OUTPUT_ARCH(arm)ENTRY(_start)SECTIONS{    ...    . = ALIGN(4);    __bss_start = .;    .bss : { *(.bss) }    _end = .;}  4)common/lcd.c: lcd_setmem()入口参数:addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); see above      /* * This is called early in the system initialization to grab memory * for the LCD controller. * Returns new address for monitor, after reserving LCD buffer memory * * Note that this is running from ROM, so no write access to global data. */ulong lcd_setmem (ulong addr){    ulong size;    int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;    debug ("LCD panel info: %d x %d, %d bit/pix\n",        panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) );    size = line_length * panel_info.vl_row;    /* Round up to nearest full page */    size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);    /* Allocate pages for the frame buffer. */    addr -= size;    debug ("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr);    return (addr);}===>这里没有支持6410的LCD,故,也无定义s3c6410的控制器的结构,也无初始化      ===>panel_infovidinfo_t panel_info;   ===>vidinfo_t:include/lcd.h#if defined CONFIG_MPC823/* * LCD controller stucture for MPC823 CPU */typedef struct vidinfo {    ushort    vl_col;        /* Number of columns (i.e. 640) */    ushort    vl_row;        /* Number of rows (i.e. 480) */    ushort    vl_width;    /* Width of display area in millimeters */    ushort    vl_height;    /* Height of display area in millimeters */    /* LCD configuration register */    u_char    vl_clkp;    /* Clock polarity */    u_char    vl_oep;        /* Output Enable polarity */    u_char    vl_hsp;        /* Horizontal Sync polarity */    u_char    vl_vsp;        /* Vertical Sync polarity */    u_char    vl_dp;        /* Data polarity */    u_char    vl_bpix;    /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */    u_char    vl_lbw;        /* LCD Bus width, 0 = 4, 1 = 8 */    u_char    vl_splt;    /* Split display, 0 = single-scan, 1 = dual-scan */    u_char    vl_clor;    /* Color, 0 = mono, 1 = color */    u_char    vl_tft;        /* 0 = passive, 1 = TFT */    /* Horizontal control register. Timing from data sheet */    ushort    vl_wbl;        /* Wait between lines */    /* Vertical control register */    u_char    vl_vpw;        /* Vertical sync pulse width */    u_char    vl_lcdac;    /* LCD AC timing */    u_char    vl_wbf;        /* Wait between frames */} vidinfo_t;extern vidinfo_t panel_info;#elif defined CONFIG_PXA250/* * PXA LCD info */struct pxafb_info {    /* Misc registers */    u_long    reg_lccr3;    u_long    reg_lccr2;    u_long    reg_lccr1;    u_long    reg_lccr0;    u_long    fdadr0;    u_long    fdadr1;    /* DMA descriptors */    struct    pxafb_dma_descriptor *    dmadesc_fblow;    struct    pxafb_dma_descriptor *    dmadesc_fbhigh;    struct    pxafb_dma_descriptor *    dmadesc_palette;    u_long    screen;        /* physical address of frame buffer */    u_long    palette;    /* physical address of palette memory */    u_int    palette_size;};/* * LCD controller stucture for PXA CPU */typedef struct vidinfo {    ushort    vl_col;        /* Number of columns (i.e. 640) */    ushort    vl_row;        /* Number of rows (i.e. 480) */    ushort    vl_width;    /* Width of display area in millimeters */    ushort    vl_height;    /* Height of display area in millimeters */    /* LCD configuration register */    u_char    vl_clkp;    /* Clock polarity */    u_char    vl_oep;        /* Output Enable polarity */    u_char    vl_hsp;        /* Horizontal Sync polarity */    u_char    vl_vsp;        /* Vertical Sync polarity */    u_char    vl_dp;        /* Data polarity */    u_char    vl_bpix;    /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */    u_char    vl_lbw;        /* LCD Bus width, 0 = 4, 1 = 8 */    u_char    vl_splt;    /* Split display, 0 = single-scan, 1 = dual-scan */    u_char    vl_clor;    /* Color, 0 = mono, 1 = color */    u_char    vl_tft;        /* 0 = passive, 1 = TFT */    /* Horizontal control register. Timing from data sheet */    ushort    vl_hpw;        /* Horz sync pulse width */    u_char    vl_blw;        /* Wait before of line */    u_char    vl_elw;        /* Wait end of line */    /* Vertical control register. */    u_char    vl_vpw;        /* Vertical sync pulse width */    u_char    vl_bfw;        /* Wait before of frame */    u_char    vl_efw;        /* Wait end of frame */    /* PXA LCD controller params */    struct    pxafb_info pxa;} vidinfo_t;extern vidinfo_t panel_info;#elif defined(CONFIG_MCC200)typedef struct vidinfo {    ushort    vl_col;        /* Number of columns (i.e. 160) */    ushort    vl_row;        /* Number of rows (i.e. 100) */    u_char    vl_bpix;    /* Bits per pixel, 0 = 1 */} vidinfo_t;#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
10-26 05:09
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