之前做LDPC编码器时，学习了一下异步FIFO的相关知识，主要参考了http://www.cnblogs.com/aslmer/p/6114216.html，并在此基础上根据项目需求，添加了一个读控制模块。因为后面编码模块的需要，因此fifo_in模块要求满足下面功能：
a、存储输入数据
b、当fifo中存储数据的个数达到x时，产生激励信号，并连续输出这x个数据
c、当后面编码模块处于编码过程中时，禁止数据输出
d、x是根据不同编码码率而确定的，因此要时常变化(这个功能时联合其他模块共同实现的)
1、fifo_in.v 是顶层模块，作用是将各个小模块例化联系起来。
输入信号encoding是由后面编码模块产生，表示是否在编码过程中。输入信号in_length输入的数就是个数要求x，由码率选择模块产生。
输出信号start_code是给编码模块的激励信号。输出信号rd_over表示当前一串数据已经输出完毕，主要用于给码率选择模块改变x的值时用。
module fifo_in
(
//input
input wr_clk,
input encoding,
input wr_rst_n,
input wr_ask,
input [:] wr_data,
input rd_clk,
input rd_rst_n,
input [:] in_length,
//output
output wr_full,//写满
output rd_empty,//读空
output [:] rd_data,
output rd_en,
output start_code,
output rd_over
);
wire wr_en;
wire [:] wr_addr;
wire [:] rd_addr;
wire rd_ask; assign wr_en =(wr_ask) && (!wr_full);
fifo_in_control fifo_in_control
(
//input
.wr_clk(wr_clk),
.wr_rst_n(wr_rst_n),
.wr_ask(wr_ask),
//.wr_data(wr_data),
.rd_clk(rd_clk),
.rd_rst_n(rd_rst_n),
.rd_ask(rd_ask),
//output
.wr_full(wr_full),//写满
.rd_empty(rd_empty),//读空
.wr_addr(wr_addr),
.rd_addr(rd_addr)
//output [2:0] rd_data
);
fifo_in_rd_control fifo_in_rd_control
(
//input
.rd_clk(rd_clk),
.rd_rst_n(rd_rst_n),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.in_length(in_length),
.encoding(encoding),
//output
.rd_ask(rd_ask),
.start_code_1(start_code),
.rd_en_1(rd_en),
.rd_over(rd_over) );
fifo_in_mem fifo_in_mem (
.data(wr_data),
.rdaddress(rd_addr),
.rdclock(rd_clk),
.wraddress(wr_addr),
.wrclock(wr_clk),
.wren(wr_en),
.q(rd_data)
);
endmodule
2、fifo_in_control.v 是异步fifo的主要程序，我从上面那个网址抄来的，网址内的讲解也非常清楚，使用格雷码来避免读写地址的混乱。
module fifo_in_control
(
//input
input wr_clk,
input wr_rst_n,
input wr_ask,
//input [2:0] wr_data,
input rd_clk,
input rd_rst_n,
input rd_ask,
//output
output reg wr_full,//写满
output reg rd_empty,//读空
output [:] wr_addr,
output [:] rd_addr
//output [2:0] rd_data
); reg [:] rd_proint_gray;//格雷码形式的写指针
reg [:] rd_proint_gray_1;//格雷码形式的写指针_延时一个写时钟
reg [:] rd_proint_gray_2;//格雷码形式的写指针_延时两个写时钟（同步到写时钟的读指针） reg [:] wr_proint_gray;//格雷码形式的读指针
reg [:] wr_proint_gray_1;//格雷码形式的读指针_延时一个读时钟
reg [:] wr_proint_gray_2;//格雷码形式的读指针_延时两个读时钟（同步到读时钟的写指针） reg [:] wr_proint_bin;//二进制形式的写指针
wire [:] wr_proint_bin_next;
wire [:] wr_proint_gray_next;
wire wr_full_val; reg [:] rd_proint_bin;//二进制形式的读指针
wire [:] rd_proint_bin_next;
wire [:] rd_proint_gray_next;
wire rd_empty_val;
//---------------------------------------------------------------------------------
always @(posedge wr_clk or negedge wr_rst_n)//读指针同步到写时钟
begin
if (!wr_rst_n)
begin
rd_proint_gray_1 <= ;
rd_proint_gray_2 <= ;
end
else
begin
rd_proint_gray_1 <= rd_proint_gray;
rd_proint_gray_2 <= rd_proint_gray_1;
end
end
//--------------------------------------------------------------------------------
always @(posedge rd_clk or negedge rd_rst_n)//写指针同步到读时钟
begin
if (!rd_rst_n)
begin
wr_proint_gray_1 <= ;
wr_proint_gray_2 <= ;
end
else
begin
wr_proint_gray_1 <= wr_proint_gray;
wr_proint_gray_2 <= wr_proint_gray_1;
end
end
//---------------------------------------------------------------------------------
//写满判决
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (!wr_rst_n)
{wr_proint_bin, wr_proint_gray} <= ;
else
{wr_proint_bin, wr_proint_gray} <= {wr_proint_bin_next, wr_proint_gray_next};
end // Memory write-address pointer (okay to use binary to address memory)
assign wr_addr = wr_proint_bin[:];
assign wr_proint_bin_next = wr_proint_bin + (wr_ask & ~wr_full);
assign wr_proint_gray_next = (wr_proint_bin_next>>) ^ wr_proint_bin_next; //二进制转为格雷码
assign wr_full_val = (wr_proint_gray_next=={~rd_proint_gray_2[:],rd_proint_gray_2[:]}); //当最高位和次高位不同其余位相同时则写指针超前于读指针一圈，即写满 always @(posedge wr_clk or negedge wr_rst_n)
begin
if (!wr_rst_n)
wr_full <= 'b0;
else
wr_full <= wr_full_val;
end
//----------------------------------------------------------------------------------
//读空判决
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (!rd_rst_n)
begin
rd_proint_bin <= ;
rd_proint_gray <= ;
end
else
begin
rd_proint_bin <= rd_proint_bin_next; //直接作为存储实体的地址
rd_proint_gray <= rd_proint_gray_next;
end
end
// Memory read-address pointer (okay to use binary to address memory)
assign rd_addr = rd_proint_bin[:]; //直接作为存储实体的地址
assign rd_proint_bin_next = rd_proint_bin + (rd_ask & ~rd_empty);//不空且有读请求的时候读指针加1
assign rd_proint_gray_next = (rd_proint_bin_next>>) ^ rd_proint_bin_next;//将二进制的读指针转为格雷码
// FIFO empty when the next rptr == synchronized wptr or on reset
assign rd_empty_val = (rd_proint_gray_next == wr_proint_gray_2); //当读指针等于同步后的写指针，则为空。 always @(posedge rd_clk or negedge rd_rst_n)
begin
if (!rd_rst_n)
rd_empty <= 'b1;
else
rd_empty <= rd_empty_val;
end endmodule
3、fifo_in_rd_control.v 是fifo_in的读控制模块，状态机分为五个状态。数据length记录当前fifo中存储数据的个数，当其大于x(in_length)时，可以进行输出。当fifo中存储数据的个数一直大于x时，两串输出数据的间隔只有几个时钟周期，有时会造成encoding信号还没有生效，新的一串数据已经开始输出，因此设置delay状态，稍等几个周期，确定编码模块是否在工作。
module fifo_in_rd_control
(
//input
input rd_clk,
input rd_rst_n,
input [:] rd_addr,
input [:] wr_addr,
input [:] in_length,
input encoding,
//output
output reg rd_ask,
output reg start_code_1,
output reg rd_en_1,
output reg rd_over
);
reg [:] length;//当前fifo中存储数据的个数
reg [:] state;
reg [:] count;//计输出数据的个数
// reg [9:0] in_length_next;
//reg rd_over;
reg start_code;
reg rd_en;
reg [:]i;//延时几个时钟 parameter hold = 'b00001;
parameter delay = 'b00010;
parameter start = 'b00100;
parameter read = 'b01000;
parameter over = 'b10000; always @(posedge rd_clk or negedge rd_rst_n)
begin
start_code_1 <= start_code;
rd_en_1 <= rd_en;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(!rd_rst_n)
begin
state <= hold;
rd_ask <= ;
start_code <= ;
rd_en <= ;
rd_over <= ;
end
else if(encoding)
begin
state <= hold;
rd_ask <= ;
start_code <= ;
rd_en <= ;
rd_over <= ;
end
else
case(state)
hold:
if(in_length <= length)
begin
state <= delay;
rd_over <= ;
i <= 'b00;
end
else
begin
state <= hold;
rd_over <= ;
end
delay:
if(i >= )
state <= start;
else
i <= i + ;
start:
begin
state <= read;
start_code <= ;
end
read:
if(count == in_length-)
begin
state <= over;
rd_en <= ;
rd_ask <= ;
end
else
begin
state <= read;
rd_en <= ;
rd_ask <= ;
start_code <= ;
end
over:
begin
state <= hold;
rd_over <= ;
end
default:state <= hold;
endcase
end always @(posedge rd_clk or negedge rd_rst_n)
begin
if(!rd_rst_n)
length <= ;
else if(wr_addr < rd_addr)
length <= ('d1023 ^ rd_addr) + wr_addr + 10'd1;
else
length <= wr_addr - rd_addr;
end always @(posedge rd_clk or negedge rd_rst_n)
begin
if(!rd_rst_n)
count <= 'd0;
else if(rd_en)
count <= count + 'd1;
else if(start_code)
count <= 'd0;
else
count <= count;
end // always @(posedge rd_clk or negedge rd_rst_n)
// begin
// if(!rd_rst_n)
// in_length_next <= in_length;
// else if(rd_over)
// in_length_next <= in_length;
// else
// in_length_next <= in_length_next;
// end endmodule
4、fifo_in_mem.v 生成存储实体，FIFO 的本质是RAM,因此在设计存储实体的时候有两种方法：用数组存储数据或者调用RAM的IP核。我是采用IP核的方法。
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram // ============================================================
// File Name: fifo_in_mem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Standard Edition
// ************************************************************ //Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details. // synopsys translate_off
`timescale ps / ps
// synopsys translate_on
module fifo_in_mem (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q); input [:] data;
input [:] rdaddress;
input rdclock;
input [:] wraddress;
input wrclock;
input wren;
output [:] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif wire [:] sub_wire0;
wire [:] q = sub_wire0[:]; altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 ('b0),
.aclr1 ('b0),
.addressstall_a ('b0),
.addressstall_b ('b0),
.byteena_a ('b1),
.byteena_b ('b1),
.clocken0 ('b1),
.clocken1 ('b1),
.clocken2 ('b1),
.clocken3 ('b1),
.data_b ({{'b1}}),
.eccstatus (),
.q_a (),
.rden_a ('b1),
.rden_b ('b1),
.wren_b ('b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = ,
altsyncram_component.numwords_b = ,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = ,
altsyncram_component.widthad_b = ,
altsyncram_component.width_a = ,
altsyncram_component.width_b = ,
altsyncram_component.width_byteena_a = ; endmodule // ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "3072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL "data[2..0]"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 3 0 data 0 0 3 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_b 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_in_mem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_in_mem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_in_mem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_in_mem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_in_mem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_in_mem_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
5、fifo_in_vlg_tst.vt 测试文件
`timescale ps/ ps
module fifo_in_vlg_tst(); // test vector input registers
reg [:] in_length;
reg rd_clk;
reg rd_rst_n;
reg wr_ask;
reg wr_clk;
reg [:] wr_data;
reg wr_rst_n;
reg encoding;
// wires
wire [:] rd_data;
wire rd_empty;
wire rd_en;
wire start_code;
wire wr_full; //malv 1/2
reg [:] din_1_2_1;
reg [:] din_1_2_2;
//malv 2/3
reg [:] din_2_3_1;
reg [:] din_2_3_2;
//malv 3/4
reg [:] din_3_4_1;
reg [:] din_3_4_2; reg [:] din; integer i;
// assign statements (if any)
fifo_in i1 (
// port map - connection between master ports and signals/registers
.in_length(in_length),
.rd_clk(rd_clk),
.rd_data(rd_data),
.rd_empty(rd_empty),
.rd_en(rd_en),
.rd_rst_n(rd_rst_n),
.encoding(encoding),
.start_code(start_code),
.wr_ask(wr_ask),
.wr_clk(wr_clk),
.wr_data(wr_data),
.wr_full(wr_full),
.wr_rst_n(wr_rst_n)
);
initial
begin
din_1_2_1= 'O 216071251457553141656632576654636070430546464764636272066726436705132675575435232347124324703044614365222721255502724213676021274561705551344656470423514271071110356653574261134400253673045231;
din_1_2_2= 'O 734100661755703340504534153032144316624677316012644740643223101214666566170511214734453676261445357016337671034473372575240732732041042256277164745532035241257613727416542012571673163075070075; din = 'o 216071251457553141656632576654636070430546464764636272066726436705132675575435232347124324703044614365222721255502724213676021274561705551344656470423514271071110356653574261134400253673045231542501077035264326753724722702415645614046732574710233250322042102460716671431441473530262042546610650744466305262611705533733122712351603065154647323273235316421143506516144106630415427670155643465425347677600020324722621463553370234733536333100716567137573041454431304700710617024455316156070660472646602537542273606077401560672521652430032221351533114247557647027635331303274633674616747411356624001531310647546770647436137465415055577647400636145042031011105245343036621453170011440755067766413107222350646230152707457233660120421175370554142117010307102307220204650067406225005445562543062450143765000675150052554515760225462106134153160214030062473563507126363205334026511003554051101112212754110754214712305373413166252464223324533002257731665505310611574517450650424331207571764326106555336266645730652715431031526541727120510525350765634442131670406707056477511100472377576251254346444405727273311256506760355125341166701031700462121475030437637137754734100661755703340504534153032144316624677316012644740643223101214666566170511214734453676261445357016337671034473372575240732732041042256277164745532035241257613727416542012571673163075070075245625704322671617635362047135076413476753731354677470024474345061322512112733173643763673247535744201030750013105263300041667311462357154373154267711040374213703605721574716231645607365613476744607305114223334110261556622426642513347671406467730411205542647724246516035625711122704161472013217573704617664621246236471651334606623455633746244704407736142361232671153775635747535713735775004475542740540721021502273646076032514443043033465601376320541316270654550702170455606451457300565274701676216621266442563332577525101140657357427027220712734450406261470005406400160110655754767533701340570327421466614606710363341164260352347602363143776557020642142000303720472010535545757310525545433730156716434355206361077760474607743250274332774733116546441410541354110331500770361665037535147625270260465132341751476532412776714575356407040361753126054573276304142254615065707442061247471350536327530550073001734307224325742130741406344520305075741267260435203513562; din_2_3_1= 'O 542501077035264326753724722702415645614046732574710233250322042102460716671431441473530262042546610650744466305262611705533733122712351603065154647323273235316421143506516144106630415427670155643465425347677600020324722621463553370234733536333100716567137573041454431304700710617024455316156070660472646602537542273606077401560672521652430032221351533114247557647027635331303274633674;
din_2_3_2= 'O 754767533701340570327421466614606710363341164260352347602363143776557020642142000303720472010535545757310525545433730156716434355206361077760474607743250274332774733116546441410541354110331500770361665037535147625270260465132341751476532412776714575356407040361753126054573276304142254615065707442061247471350536327530550073001734307224325742130741406344520305075741267260435203513562; din_3_4_1= 'O 616747411356624001531310647546770647436137465415055577647400636145042031011105245343036621453170011440755067766413107222350646230152707457233660120421175370554142117010307102307220204650067406225005445562543062450143765000675150052554515760225462106134153160214030062473563507126363205334026511003554051101112212754110754214712305373413166252464223324533002257731665505310611574517450650424331207571764326106555336266645730652715431031526541727120510525350765634442131670406707056477511100472377576251254346444405727273311256506760355125341166701031700462121475030437637137754;
din_3_4_2= 'O 245625704322671617635362047135076413476753731354677470024474345061322512112733173643763673247535744201030750013105263300041667311462357154373154267711040374213703605721574716231645607365613476744607305114223334110261556622426642513347671406467730411205542647724246516035625711122704161472013217573704617664621246236471651334606623455633746244704407736142361232671153775635747535713735775004475542740540721021502273646076032514443043033465601376320541316270654550702170455606451457300565274701676216621266442563332577525101140657357427027220712734450406261470005406400160110655; in_length = 'd576;
encoding = ;
rd_clk = ;
wr_clk = ;
rd_rst_n = ;
wr_rst_n = ;
wr_ask = ;
wr_data = 'd0;
#
rd_rst_n = ;
wr_rst_n = ;
#
rd_rst_n = ;
wr_rst_n = ;
// #2000
// in_length = 10'd384;
end
// initial
// begin
// #63950
// encoding = 1;
// #5000
// encoding = 0;
// end
// initial
// begin
// #30000
// in_length = 10'd576;
// end
// initial
// begin
// #60000
// in_length = 10'd192;
// end
// initial
// begin
// #83000
// in_length = 10'd576;
// end always # rd_clk <= ~rd_clk;
always # wr_clk <= ~wr_clk; initial
begin
#
for(i = ; i >=; i = i-)
begin
wr_data[] <= din[i];
wr_data[] <= din[i-];
wr_data[] <= din[i-];
#;
end
end always @ (i)
begin
if (i < )
wr_ask = ;
else
wr_ask = ;
end endmodule
仿真结果